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feat(codegen-x86): Switch to using x86::codegen from arch-ops
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@chorman0773
chorman0773 committed Sep 22, 2023
1 parent ddaed59 commit c321d58
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Showing 2 changed files with 28 additions and 48 deletions.
74 changes: 27 additions & 47 deletions codegen-x86/src/mc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@ use std::{ops::Deref, rc::Rc, str::FromStr};
use arch_ops::{
traits::{Address, InsnWrite},
x86::{
codegen::{X86CodegenOpcode, X86Encoder, X86Instruction, X86MemoryOperand, X86Operand},
features::X86Feature,
insn::{X86Encoder, X86Instruction, X86Mode, X86Opcode, X86Operand},
X86Register, X86RegisterClass,
X86Mode, X86Register, X86RegisterClass,
},
};
use target_tuples::Architecture;
Expand Down Expand Up @@ -588,20 +588,12 @@ impl MCWriter for X86MCWriter {
) if destreg.class() == srcreg.class() => match destreg.class()
{
arch_ops::x86::X86RegisterClass::Byte
| arch_ops::x86::X86RegisterClass::ByteRex => {
encoder.write_insn(X86Instruction::new(
X86Opcode::MovMR8,
vec![
X86Operand::Register(*destreg),
X86Operand::Register(*srcreg),
],
))?;
}
arch_ops::x86::X86RegisterClass::Word
| arch_ops::x86::X86RegisterClass::ByteRex
| arch_ops::x86::X86RegisterClass::Word
| arch_ops::x86::X86RegisterClass::Double
| arch_ops::x86::X86RegisterClass::Quad => {
encoder.write_insn(X86Instruction::new(
X86Opcode::MovMR,
X86CodegenOpcode::Mov,
vec![
X86Operand::Register(*destreg),
X86Operand::Register(*srcreg),
Expand Down Expand Up @@ -633,42 +625,24 @@ impl MCWriter for X86MCWriter {
X86ValLocation::Null => {}
X86ValLocation::Register(reg) => match reg.class() {
arch_ops::x86::X86RegisterClass::Byte
| arch_ops::x86::X86RegisterClass::ByteRex => {
if *src == 0 {
encoder.write_insn(X86Instruction::new(
X86Opcode::XorMR8,
vec![
X86Operand::Register(*reg),
X86Operand::Register(*reg),
],
))?;
} else {
encoder.write_insn(X86Instruction::new(
X86Opcode::MovImm8,
vec![
X86Operand::Register(*reg),
X86Operand::Immediate(*src as u64),
],
))?;
}
}
arch_ops::x86::X86RegisterClass::Word
| arch_ops::x86::X86RegisterClass::ByteRex
| arch_ops::x86::X86RegisterClass::Word
| arch_ops::x86::X86RegisterClass::Double
| arch_ops::x86::X86RegisterClass::Quad => {
if *src == 0 {
encoder.write_insn(X86Instruction::new(
X86Opcode::XorMR,
X86CodegenOpcode::Xor,
vec![
X86Operand::Register(*reg),
X86Operand::Register(*reg),
],
))?;
} else {
encoder.write_insn(X86Instruction::new(
X86Opcode::MovImm,
X86CodegenOpcode::Mov,
vec![
X86Operand::Register(*reg),
X86Operand::Immediate(*src as u64),
X86Operand::Immediate(*src as i64),
],
))?;
}
Expand Down Expand Up @@ -707,41 +681,47 @@ impl MCWriter for X86MCWriter {
frame_size += disp;

encoder.write_insn(X86Instruction::new(
X86Opcode::SubImm,
X86CodegenOpcode::Sub,
vec![
X86Operand::Register(X86Register::Rsp),
X86Operand::Immediate(disp as u64),
X86Operand::Immediate(disp as i64),
],
))?;
}

encoder.write_insn(X86Instruction::new(
X86Opcode::Call,
vec![X86Operand::RelAddr(Address::PltSym { name: sym.clone() })],
X86CodegenOpcode::Call,
vec![X86Operand::RelOffset(Address::PltSym { name: sym.clone() })],
))?;
}
MCInsn::Return => {
if frame_size > 0 {
encoder.write_insn(X86Instruction::new(
X86Opcode::AddImm,
X86CodegenOpcode::Add,
vec![
X86Operand::Register(X86Register::Rsp),
X86Operand::Immediate(frame_size as u64),
X86Operand::Immediate(frame_size as i64),
],
))?;
}
encoder.write_insn(X86Instruction::Retn)?;
encoder.write_insn(X86Instruction::Ret)?;
}
MCInsn::LoadSym { loc, sym } => match loc {
MaybeResolved::Resolved(_, loc) => match loc {
X86ValLocation::Register(reg) => match reg.class() {
X86RegisterClass::Word
| X86RegisterClass::Double
| X86RegisterClass::Quad => encoder.write_insn(X86Instruction::new(
X86Opcode::Lea,
X86CodegenOpcode::Lea,
vec![
X86Operand::Register(*reg),
X86Operand::RelAddr(Address::PltSym { name: sym.clone() }),
X86Operand::Memory(
reg.class(),
None,
X86MemoryOperand::RelAddr(Address::PltSym {
name: sym.to_string(),
}),
),
],
))?,
_ => todo!(),
Expand All @@ -754,8 +734,8 @@ impl MCWriter for X86MCWriter {
sym_accepter(label.clone(), encoder.offset() as u64);
}
MCInsn::UnconditionalBranch(label) => encoder.write_insn(X86Instruction::new(
X86Opcode::Jmp,
vec![X86Operand::RelAddr(Address::Symbol {
X86CodegenOpcode::Jmp,
vec![X86Operand::RelOffset(Address::Symbol {
name: label.clone(),
disp: 0,
})],
Expand Down
2 changes: 1 addition & 1 deletion lc-binutils
Submodule lc-binutils updated 8 files
+7 −0 Cargo.lock
+2 −1 arch-ops/Cargo.toml
+3 −0 arch-ops/src/traits.rs
+88 −6 arch-ops/src/x86.rs
+1,743 −0 arch-ops/src/x86/codegen.rs
+485 −0 arch-ops/src/x86/codegen/insn.rs
+6 −1 arch-ops/src/x86/features.rs
+1 −44 arch-ops/src/x86/insn.rs

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