Put IO into top level and do address decoding

Makefile

@@ -27,6 +27,8 @@ TESTPATH=asm/test
 hwsim:
 	sbt -Dprogram=$(APP) "testOnly leros.LerosTest"
 
+sim-blink:
+	sbt -Dprogram=blink -Dtestpath=asm "testOnly leros.LerosTest"
 
 swsim:
 	sbt -Dprogram=$(APP) "testOnly leros.sim.LerosSimTest"

TODO.md

@@ -43,7 +43,7 @@
  - [ ] Check if write in Chisel/Verilog is not through a register
     * wondering on timing and layout in Quartus
  - [ ] Get rid of code duplication in Decode
- - [ ] Do memory mapped IO
+ - [x] Do memory mapped IO
  - [ ] Be able to simulate source in asm
  - [x] Setup FPGA (Nexys A7)
    - [x] Use chipdesign1 for synthesis, OpenOCD for configuration
@@ -60,7 +60,7 @@
  - [ ] Any instruction not used by the compiler? 
  - [ ] load/store byte indirect 
  - [ ] Does subi sign extend? Do we need a subi? We could use addi with neg. values 
- - [ ] Get a simple sequential version done 
+ - [x] Get a simple sequential version done 
  - [ ] Pipelined version follows after sequential 
  - [ ] Run Morten's C test programs 
  - [ ] gcc test suit as in Patmos

asm/blink.s

@@ -3,9 +3,15 @@
 // We need 2.500.000 iterations for a 100 ms tick
 //
 
+// set the IO base address to 0x0f00 (in bytes)
+    loadhi 0x0f
+    store r2
+    ldaddr r2
+// the counter
     loadi 0
     store r2
 loop:
+
     loadi 255
     loadhi 255
     loadh2i 38

src/main/scala/leros/Leros.scala

@@ -16,21 +16,15 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Module
     val addr = Output(UInt(memAddrWidth.W))
     val instr = Input(UInt(16.W))
   })
-  val dmemIO = IO(Flipped(new DataMemIO(memAddrWidth)))
-
-  val io = IO(new Bundle {
-    // val dout = Output(UInt(32.W))
-    // val sw = Input(UInt(4.W))
-    val led = Output(UInt(8.W))
-  })
+  val dmemIO = IO(Flipped(new DataMemIO(16)))
 
   val alu = Module(new AluAccu(size))
 
   val accu = alu.io.accu
 
   // The main architectural state
   val pcReg = RegInit(0.U(memAddrWidth.W))
-  val addrReg = RegInit(0.U(memAddrWidth.W))
+  val addrReg = RegInit(0.U(16.W))
 
   val pcNext = WireDefault(pcReg + 1.U)
 
@@ -54,7 +48,7 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Module
   for (i <- 0 until 4) {
     vecAccu(i) := accu(i*8 + 7, i*8)
   }
-  // printf("%x %x %x %x\n", effAddr, effAddrWord, effAddrOff, decout.off)
+  // printf("%x %x %x %x %x\n", addrReg, effAddr, effAddrWord, effAddrOff, decout.off)
 
   // Data memory, including the register memory
   // read in fetch, write in execute
@@ -81,8 +75,6 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Module
 
   // connection to the external world (for testing)
   val exit = RegInit(false.B)
-  val outReg = RegInit(0.U(32.W))
-  io.led := outReg
 
   val stateReg = RegInit(fetch)
 
@@ -114,9 +106,6 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Module
 
     is (storeInd) {
       dmemIO.wr := true.B
-      // TODO: am I missing here something? See the other store indirect
-      // TODO: this is a super quick hack to get the LED blinking
-      outReg := accu
     }
 
     is (storeIndB) {

src/main/scala/leros/LerosTop.scala

@@ -29,7 +29,13 @@ class LerosTop(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends Modu
   dataMem.io <> leros.dmemIO
 
   // TODO: LED and decoding for it
-  io.led := leros.io.led
+  val ledReg = RegInit(0.U(8.W))
+  io.led := ledReg
+  // IO is now mapped to 0x0f00, but wrAddr counts in 32-bit words
+  when((leros.dmemIO.wrAddr === 0x03c0.U) &&  leros.dmemIO.wr) {
+    ledReg := leros.dmemIO.wrData(7, 0)
+    dataMem.io.wr := false.B
+  }
 }
 
 object LerosTop extends App {

src/test/scala/leros/LerosTest.scala

@@ -19,7 +19,7 @@ class LerosTest extends AnyFlatSpec with ChiselScalatestTester {
 
     def testFun(dut: LerosTestTop): Unit = {
       var run = true
-      var maxCycles = 10000
+      var maxCycles = 1000
       while (run) {
         val pc = dut.io.dbg.pc.peekInt()
         val accu = dut.io.dbg.accu.peekInt()