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Merge pull request ARMmbed#50 from linlingao/spi_port
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Add the 1st draft of SPI HAL driver. Fix more compiler warnings.
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linlingao authored Aug 14, 2018
2 parents 99d6ce3 + 1ca3235 commit c4e3923
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Showing 9 changed files with 573 additions and 16 deletions.
12 changes: 12 additions & 0 deletions targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PinNames.h
Original file line number Diff line number Diff line change
Expand Up @@ -121,6 +121,18 @@ typedef enum {
BUTTON1 = PIN_04,
BUTTON2 = PIN_15,

//SPI1
SPICC32XXDMA_MOSI = P07,
SPICC32XXDMA_MISO = P06,
SPICC32XXDMA_CLK = P05,
SPICC32XXDMA_CS = P08,

// CI Shield
D10 = SPICC32XXDMA_CS,
D11 = SPICC32XXDMA_MOSI,
D12 = SPICC32XXDMA_MISO,
D13 = SPICC32XXDMA_CLK,

// Not connected
NC = (int)0xFFFFFFFF,
PIN_RESERVED = NC,
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Expand Up @@ -68,16 +68,6 @@ const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
*/
void CC3220SF_LAUNCHXL_initGeneral(void)
{
PRCMPeripheralReset(PRCM_TIMERA0);
PRCMPeripheralReset(PRCM_TIMERA1);
PRCMPeripheralReset(PRCM_TIMERA2);
PRCMPeripheralReset(PRCM_TIMERA3);
PRCMPeripheralReset(PRCM_UARTA0);
PRCMPeripheralReset(PRCM_UARTA1);
PRCMPeripheralReset(PRCM_GPIOA0);
PRCMPeripheralReset(PRCM_GPIOA1);
PRCMPeripheralReset(PRCM_GPIOA2);
PRCMPeripheralReset(PRCM_GPIOA3);
MAP_IntMasterEnable();
//MAP_IntEnable(FAULT_SYSTICK);
PRCMCC3200MCUInit();
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89 changes: 89 additions & 0 deletions targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h
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Expand Up @@ -16,6 +16,7 @@
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H

#include "stdbool.h"
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
Expand Down Expand Up @@ -60,6 +61,94 @@ struct serial_s {
UART_PAR parityType; /* Parity bit type for UART */
};

typedef struct spi_clock_config_s {

//! \param ulSPIClk is the rate of clock supplied to the SPI module.
uint32_t ulSPIClk;

//! \param ulBitRate is the desired bit rate.(master mode)
uint32_t ulBitRate;

//!
//! The SPI module can operate in either master or slave mode. The parameter
//! \e ulMode can be one of the following
//! -\b SPI_MODE_MASTER
//! -\b SPI_MODE_SLAVE
uint32_t ulMode;

//!
//! The SPI module supports 4 sub modes based on SPI clock polarity and phase.
//!
//! <pre>
//! Polarity Phase Sub-Mode
//! 0 0 0
//! 0 1 1
//! 1 0 2
//! 1 1 3
//! </pre>

//! Required sub mode can be select by setting \e ulSubMode parameter to one
//! of the following
//! - \b SPI_SUB_MODE_0
//! - \b SPI_SUB_MODE_1
//! - \b SPI_SUB_MODE_2
//! - \b SPI_SUB_MODE_3
uint32_t ulSubMode;

//! The parameter \e ulConfig is logical OR of five values: the word length,
//! active level for chip select, software or hardware controlled chip select,
//! 3 or 4 pin mode and turbo mode.
//! mode.
//!
//! SPI support 8, 16 and 32 bit word lengths defined by:-
//! - \b SPI_WL_8
//! - \b SPI_WL_16
//! - \b SPI_WL_32
//!
//! Active state of Chip Select can be defined by:-
//! - \b SPI_CS_ACTIVELOW
//! - \b SPI_CS_ACTIVEHIGH
//!
//! SPI chip select can be configured to be controlled either by hardware or
//! software:-
//! - \b SPI_SW_CS
//! - \b SPI_HW_CS
//!
//! The module can work in 3 or 4 pin mode defined by:-
//! - \b SPI_3PIN_MODE
//! - \b SPI_4PIN_MODE
//!
//! Turbo mode can be set on or turned off using:-
//! - \b SPI_TURBO_MODE_ON
//! - \b SPI_TURBO_MODE_OFF
uint32_t ulConfig;
} spi_clock_config_t;

struct spi_s {
/*! SPI module number */
uint32_t instance;

/*! SPICC32XXDMA Peripheral's base address */
uint32_t baseAddr;

/*! SPI Word lengh */
uint32_t word_length;

/*! SPI clock configuration */
spi_clock_config_t clock_config;

/*! Is clock update needed */
bool clock_update;

/*! Is CS controlled by GPIO */
bool cs_control_gpio;

#if DEVICE_SPI_ASYNCH
uint32_t handler;
uint32_t mask;
uint32_t event;
#endif
};
#ifdef __cplusplus
}
#endif
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