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refactor: moved resync to controller (#521)
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The resynce functionality has been moved to the controller. This means
the core application know how to do CRUD on the vmspecs and how to
reconcile a single vm spec.

Functionality such as resynce can be orchestrated via calls to the core
app.

Signed-off-by: Richard Case <richard.case@outlook.com>
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richardcase authored Aug 23, 2022
1 parent adddb41 commit 20fda19
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Showing 6 changed files with 17 additions and 32 deletions.
22 changes: 0 additions & 22 deletions core/application/reconcile.go
Original file line number Diff line number Diff line change
Expand Up @@ -35,28 +35,6 @@ func (a *app) ReconcileMicroVM(ctx context.Context, vmid models.VMID) error {
return a.reconcile(ctx, spec, logger)
}

func (a *app) ResyncMicroVMs(ctx context.Context, namespace string) error {
logger := log.GetLogger(ctx).WithFields(logrus.Fields{
"action": "resync",
"namespace": "ns",
})
logger.Info("Resyncing specs")
logger.Debug("Getting all specs")

specs, err := a.ports.Repo.GetAll(ctx, models.ListMicroVMQuery{"namespace": namespace})
if err != nil {
return fmt.Errorf("getting all microvm specs for resync: %w", err)
}

for _, spec := range specs {
if err := a.reconcile(ctx, spec, logger); err != nil {
return fmt.Errorf("resync reconcile for spec %s: %w", spec.ID, err)
}
}

return nil
}

func (a *app) plan(spec *models.MicroVM, logger *logrus.Entry) planner.Plan {
l := logger.WithField("stage", "plan")
l.Info("Generate plan")
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3 changes: 0 additions & 3 deletions core/ports/usecases.go
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,4 @@ type MicroVMQueryUseCases interface {
type ReconcileMicroVMsUseCase interface {
// ReconcileMicroVM is a use case for reconciling a specific microvm.
ReconcileMicroVM(ctx context.Context, vmid models.VMID) error
// ResyncMicroVMs is used to resync the microvms. If a namespace is supplied then it will
// resync only the microvms in that namespaces.
ResyncMicroVMs(ctx context.Context, namespace string) error
}
16 changes: 12 additions & 4 deletions infrastructure/controllers/microvm_controller.go
Original file line number Diff line number Diff line change
Expand Up @@ -16,17 +16,19 @@ import (
"github.com/weaveworks-liquidmetal/flintlock/pkg/queue"
)

func New(eventSvc ports.EventService, reconcileUC ports.ReconcileMicroVMsUseCase) *MicroVMController {
func New(eventSvc ports.EventService, reconcileUC ports.ReconcileMicroVMsUseCase, queryUC ports.MicroVMQueryUseCases) *MicroVMController {
return &MicroVMController{
eventSvc: eventSvc,
reconcileUC: reconcileUC,
queryUC: queryUC,
queue: queue.NewSimpleSyncQueue(),
}
}

type MicroVMController struct {
eventSvc ports.EventService
reconcileUC ports.ReconcileMicroVMsUseCase
queryUC ports.MicroVMQueryUseCases

queue queue.Queue
}
Expand Down Expand Up @@ -186,11 +188,17 @@ func (r *MicroVMController) handleEvent(envelope *ports.EventEnvelope, logger *l
func (r *MicroVMController) resyncSpecs(ctx context.Context, logger *logrus.Entry) error {
logger.Info("resyncing microvm specs")

err := r.reconcileUC.ResyncMicroVMs(ctx, "")
specs, err := r.queryUC.GetAllMicroVM(ctx, models.ListMicroVMQuery{
"Namespace": "",
})

if err != nil {
logger.Errorf("failed to resync microvms: %s", err)
return fmt.Errorf("getting all microvm specs for resync: %w", err)
}

return fmt.Errorf("resyncing microvms: %w", err)
for _, spec := range specs {
logger.Debugf("enqueing vmid %s for resync", spec.ID)
r.queue.Enqueue(spec.ID.String())
}

return nil
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3 changes: 2 additions & 1 deletion infrastructure/controllers/microvm_controller_test.go
Original file line number Diff line number Diff line change
Expand Up @@ -120,13 +120,14 @@ func TestMicroVMController(t *testing.T) {

em := mock.NewMockEventService(mockCtrl)
uc := mock.NewMockReconcileMicroVMsUseCase(mockCtrl)
quc := mock.NewMockMicroVMQueryUseCases(mockCtrl)

evtCh := make(chan *ports.EventEnvelope)
evtErrCh := make(chan error, 1)

tc.expect(em.EXPECT(), uc.EXPECT(), evtCh, evtErrCh)

controller := controllers.New(em, uc)
controller := controllers.New(em, uc, quc)

ctrlWG := sync.WaitGroup{}
ctrlWG.Add(1)
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2 changes: 1 addition & 1 deletion internal/inject/wire.go
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ func InitializeApp(cfg *config.Config, ports *ports.Collection) application.App
}

func InializeController(app application.App, ports *ports.Collection) *controllers.MicroVMController {
wire.Build(controllers.New, eventSvcFromScope, reconcileUCFromApp)
wire.Build(controllers.New, eventSvcFromScope, reconcileUCFromApp, queryUCFromApp)

return nil
}
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3 changes: 2 additions & 1 deletion internal/inject/wire_gen.go

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