sim.py: Update/Cleanup.

sim.py

@@ -11,24 +11,26 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex.build.generic_platform import *
-from litex.build.sim import SimPlatform
-from litex.build.sim.config import SimConfig
-from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict
-
-from litex.soc.interconnect.csr import *
-from litex.soc.integration.soc_core import *
-from litex.soc.integration.builder import *
-from litex.soc.interconnect import wishbone
+from litex.build.sim              import SimPlatform
+from litex.build.sim.config       import SimConfig
+from litex.build.sim.verilator    import verilator_build_args, verilator_build_argdict
+
+from litex.soc.interconnect.csr       import *
+from litex.soc.integration.soc_core   import *
+from litex.soc.integration.builder    import *
+from litex.soc.interconnect           import wishbone
 from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
 
 from litedram import modules as litedram_modules
-from litedram.phy.model import SDRAMPHYModel
-from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
+from litedram.phy.model       import SDRAMPHYModel
+from litex.tools.litex_sim    import sdram_module_nphases, get_sdram_phy_settings
 from litedram.core.controller import ControllerSettings
 
 from liteeth.phy.model import LiteEthPHYModel
-from liteeth.mac import LiteEthMAC
+from liteeth.mac       import LiteEthMAC
 
 from litex.tools.litex_json2dts_linux import generate_dts
 
@@ -59,7 +61,7 @@ def __init__(self):
 
 # Supervisor ---------------------------------------------------------------------------------------
 
-class Supervisor(Module, AutoCSR):
+class Supervisor(LiteXModule):
     def __init__(self):
         self._finish = CSR()    # Controlled from CPU.
         self.finish  = Signal() # Controlled from logic.
@@ -68,40 +70,38 @@ def __init__(self):
 # SoCLinux -----------------------------------------------------------------------------------------
 
 class SoCLinux(SoCCore):
-    def __init__(self,
+    def __init__(self, sys_clk_freq=int(100e6),
         init_memories    = False,
         sdram_module     = "MT48LC16M16",
         sdram_data_width = 32,
-        sdram_verbosity  = 0):
-
-        # Parameters.
-        sys_clk_freq = int(100e6)
-
-        # Platform.
+        sdram_verbosity  = 0
+    ):
+        # Platform ---------------------------------------------------------------------------------
         platform     = Platform()
         self.comb += platform.trace.eq(1)
 
-        # RAM Initialization.
+        # RAM Init ---------------------------------------------------------------------------------
         ram_init = []
         if init_memories:
             ram_init = get_mem_data("images/boot.json", endianness="little", offset=0x40000000)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = CRG(platform.request("sys_clk"))
+        self.crg = CRG(platform.request("sys_clk"))
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            cpu_type                 = "vexriscv_smp",
-            cpu_variant              = "linux",
-            integrated_rom_size      = 0x10000,
-            uart_name                = "sim")
+            cpu_type            = "vexriscv_smp",
+            cpu_variant         = "linux",
+            integrated_rom_size = 0x10000,
+            uart_name           = "sim",
+        )
         self.add_config("DISABLE_DELAYS")
 
         # Boot from OpenSBI.
         self.add_constant("ROM_BOOT_ADDRESS", self.bus.regions["opensbi"].origin)
 
         # Supervisor -------------------------------------------------------------------------------
-        self.submodules.supervisor = Supervisor()
+        self.supervisor = Supervisor()
 
         # SDRAM ------------------------------------------------------------------------------------
         sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
@@ -111,17 +111,20 @@ def __init__(self,
         phy_settings     = get_sdram_phy_settings(
             memtype    = sdram_module.memtype,
             data_width = sdram_data_width,
-            clk_freq   = sdram_clk_freq)
-        self.submodules.sdrphy = SDRAMPHYModel(
+            clk_freq   = sdram_clk_freq,
+        )
+        self.sdrphy = SDRAMPHYModel(
             module    = sdram_module,
             settings  = phy_settings,
             clk_freq  = sdram_clk_freq,
             verbosity = sdram_verbosity,
-            init      = ram_init)
+            init      = ram_init,
+        )
         self.add_sdram("sdram",
             phy           = self.sdrphy,
             module        = sdram_module,
-            l2_cache_size = 0)
+            l2_cache_size = 0,
+        )
         self.add_constant("SDRAM_TEST_DISABLE") # Skip SDRAM test to avoid corrupting pre-initialized contents.
 
     def generate_dts(self, board_name):
@@ -139,11 +142,11 @@ def compile_dts(self, board_name):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation")
-    parser.add_argument("--with-sdram",       action="store_true",     help="Enable SDRAM support.")
-    parser.add_argument("--sdram-module",     default="MT48LC16M16",   help="Select SDRAM chip.")
-    parser.add_argument("--sdram-data-width", default=32,              help="Set SDRAM chip data width.")
-    parser.add_argument("--sdram-verbosity",  default=0,               help="Set SDRAM checker verbosity.")
+    parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation.")
+    parser.add_argument("--with-sdram",       action="store_true",   help="Enable SDRAM support.")
+    parser.add_argument("--sdram-module",     default="MT48LC16M16", help="Select SDRAM chip.")
+    parser.add_argument("--sdram-data-width", default=32,            help="Set SDRAM chip data width.")
+    parser.add_argument("--sdram-verbosity",  default=0,             help="Set SDRAM checker verbosity.")
     VexRiscvSMP.args_fill(parser)
     verilator_build_args(parser)
     args = parser.parse_args()
@@ -154,22 +157,21 @@ def main():
     sim_config.add_module("serial2console", "serial")
 
     for i in range(2):
+        prepare = (i == 0)
+        run     = (i == 1)
         soc = SoCLinux(
-            init_memories    = i!=0,
+            init_memories    = run,
             sdram_module     = args.sdram_module,
             sdram_data_width = int(args.sdram_data_width),
             sdram_verbosity  = int(args.sdram_verbosity)
         )
         board_name = "sim"
         build_dir  = os.path.join("build", board_name)
         builder = Builder(soc, output_dir=build_dir,
-            compile_gateware = i != 0 ,
+            compile_gateware = run,
             csr_json         = os.path.join(build_dir, "csr.json"))
-        builder.build(sim_config=sim_config,
-            run = i != 0,
-            **verilator_build_kwargs
-        )
-        if i == 0:
+        builder.build(sim_config=sim_config, run=run, **verilator_build_kwargs)
+        if prepare:
             soc.generate_dts(board_name)
             soc.compile_dts(board_name)