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support multiple cs_n pins #80

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support multiple cs_n pins #80

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3f609ae
phy: sdr: improve phy
maass-hamburg Oct 24, 2024
66cb9cc
support multiple cs_n
maass-hamburg Oct 24, 2024
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15 changes: 10 additions & 5 deletions litespi/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -71,17 +71,21 @@ class LiteSPI(LiteXModule):
def __init__(self, phy, clock_domain="sys",
with_mmap=True, mmap_endianness="big",
with_master=True, master_tx_fifo_depth=1, master_rx_fifo_depth=1,
with_csr=True, with_mmap_write=False):
with_csr=True, with_mmap_write=False, mmap_cs_mask=1):

self.crossbar = crossbar = LiteSPICrossbar(clock_domain)
cs_width=len(phy.cs)

self.crossbar = crossbar = LiteSPICrossbar(clock_domain, cs_width)
self.comb += phy.cs.eq(crossbar.cs)

if with_mmap:
self.mmap = mmap = LiteSPIMMAP(flash=phy.flash,
endianness=mmap_endianness,
with_csr=with_csr,
with_write=with_mmap_write)
port_mmap = crossbar.get_port(mmap.cs)
with_write=with_mmap_write,
cs_width=cs_width,
cs_mask=mmap_cs_mask)
port_mmap = crossbar.get_port(mmap.cs, mmap.request)
self.bus = mmap.bus
self.comb += [
port_mmap.source.connect(mmap.sink),
Expand All @@ -92,7 +96,8 @@ def __init__(self, phy, clock_domain="sys",
if with_master:
self.master = master = LiteSPIMaster(
tx_fifo_depth = master_tx_fifo_depth,
rx_fifo_depth = master_rx_fifo_depth)
rx_fifo_depth = master_rx_fifo_depth,
cs_width = cs_width)
port_master = crossbar.get_port(master.cs)
self.comb += [
port_master.source.connect(master.sink),
Expand Down
7 changes: 5 additions & 2 deletions litespi/core/mmap.py
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Original file line number Diff line number Diff line change
Expand Up @@ -75,11 +75,12 @@ class LiteSPIMMAP(LiteXModule):
write_config : CSRStorage
Optional register holding configuration bits for the write mode.
"""
def __init__(self, flash, clock_domain="sys", endianness="big", with_csr=True, with_write=False):
def __init__(self, flash, clock_domain="sys", endianness="big", with_csr=True, with_write=False, cs_width=1, cs_mask=1):
self.source = source = stream.Endpoint(spi_core2phy_layout)
self.sink = sink = stream.Endpoint(spi_phy2core_layout)
self.bus = bus = wishbone.Interface()
self.cs = cs = Signal()
self.cs = Signal(cs_width)
self.request = cs = Signal()
self.offset = offset = Signal(len(bus.adr))

# Burst Control.
Expand Down Expand Up @@ -123,6 +124,8 @@ def __init__(self, flash, clock_domain="sys", endianness="big", with_csr=True, w
self.byte_count = byte_count = Signal(2, reset_less=True)
self.data_write = Signal(32)

self.comb += If(self.request, self.cs.eq(cs_mask))

# FSM.
self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
Expand Down
6 changes: 3 additions & 3 deletions litespi/crossbar.py
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ def __init__(self):


class LiteSPICrossbar(Module):
def __init__(self, cd):
def __init__(self, cd, cs_width=1):
self.cd = cd
self.users = []
self.master = LiteSPIMasterPort()
Expand All @@ -41,7 +41,7 @@ def __init__(self, cd):
self.master.source.connect(self.tx_cdc.sink),
]

self.cs = Signal()
self.cs = Signal(cs_width)
self.user_cs = []
self.user_request = []

Expand All @@ -59,7 +59,7 @@ def get_port(self, cs, request = None):

if request is None:
request = Signal()
self.comb += request.eq(cs)
self.comb += request.eq(cs != 0)

self.users.append(internal_port)
self.user_cs.append(self.cs.eq(cs))
Expand Down
12 changes: 8 additions & 4 deletions litespi/phy/generic_ddr.py
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@

from litex.soc.interconnect import stream

from litex.build.io import DDRTristate
from litex.build.io import DDRTristate, SDROutput

# LiteSPI DDR PHY Core -----------------------------------------------------------------------------

Expand Down Expand Up @@ -54,7 +54,7 @@ class LiteSPIDDRPHYCore(LiteXModule):
def __init__(self, pads, flash, cs_delay, extra_latency=0):
self.source = source = stream.Endpoint(spi_phy2core_layout)
self.sink = sink = stream.Endpoint(spi_core2phy_layout)
self.cs = Signal()
self.cs = Signal().like(pads.cs_n)

if hasattr(pads, "miso"):
bus_width = 1
Expand All @@ -75,9 +75,13 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
# CS control.
self.cs_timer = cs_timer = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
cs_enable = Signal()
self.comb += cs_timer.wait.eq(self.cs)
self.comb += cs_timer.wait.eq(self.cs != 0)
self.comb += cs_enable.eq(cs_timer.done)
self.comb += pads.cs_n.eq(~cs_enable)
for i in range(len(pads.cs_n)):
self.specials += SDROutput(
i = ~(cs_enable & self.cs[i]),
o = pads.cs_n[i]
)

# I/Os.
data_bits = 32
Expand Down
37 changes: 17 additions & 20 deletions litespi/phy/generic_sdr.py
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ class LiteSPISDRPHYCore(LiteXModule):
def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay):
self.source = source = stream.Endpoint(spi_phy2core_layout)
self.sink = sink = stream.Endpoint(spi_core2phy_layout)
self.cs = Signal()
self.cs = Signal().like(pads.cs_n)
self._spi_clk_divisor = spi_clk_divisor = Signal(8)

self._default_divisor = default_divisor
Expand Down Expand Up @@ -94,13 +94,13 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
# CS control.
self.cs_timer = cs_timer = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
cs_enable = Signal()
self.comb += cs_timer.wait.eq(self.cs)
self.comb += cs_timer.wait.eq(self.cs != 0)
self.comb += cs_enable.eq(cs_timer.done)
self.comb += pads.cs_n.eq(~cs_enable)

# I/Os.
data_bits = 32
cmd_bits = 8
for i in range(len(pads.cs_n)):
self.specials += SDROutput(
i = ~(cs_enable & self.cs[i]),
o = pads.cs_n[i]
)

if hasattr(pads, "mosi"):
dq_o = Signal()
Expand All @@ -115,9 +115,9 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
o = dq_i[1]
)
else:
dq_o = Signal(len(pads.dq))
dq_i = Signal(len(pads.dq))
dq_oe = Signal(len(pads.dq))
dq_o = Signal().like(pads.dq)
dq_i = Signal().like(pads.dq)
dq_oe = Signal().like(pads.dq)
for i in range(len(pads.dq)):
self.specials += SDRTristate(
io = pads.dq[i],
Expand All @@ -130,13 +130,12 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
sr_cnt = Signal(8, reset_less=True)
sr_out_load = Signal()
sr_out_shift = Signal()
sr_out = Signal(len(sink.data), reset_less=True)
sr_out = Signal().like(sink.data)
sr_in_shift = Signal()
sr_in = Signal(len(sink.data), reset_less=True)
sr_in = Signal().like(sink.data)

# Data Out Generation/Load/Shift.
self.comb += [
dq_oe.eq(sink.mask),
Case(sink.width, {
1 : dq_o.eq(sr_out[-1:]),
2 : dq_o.eq(sr_out[-2:]),
Expand All @@ -145,15 +144,11 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
})
]
self.sync += If(sr_out_load,
sr_out.eq(sink.data << (len(sink.data) - sink.len))
sr_out.eq(sink.data << (len(sink.data) - sink.len)),
sr_in.eq(0),
)
self.sync += If(sr_out_shift,
Case(sink.width, {
1 : sr_out.eq(Cat(Signal(1), sr_out)),
2 : sr_out.eq(Cat(Signal(2), sr_out)),
4 : sr_out.eq(Cat(Signal(4), sr_out)),
8 : sr_out.eq(Cat(Signal(8), sr_out)),
})
sr_out.eq(sr_out << sink.width),
)

# Data In Shift.
Expand All @@ -173,6 +168,7 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
If(cs_enable & sink.valid,
# Load Shift Register Count/Data Out.
NextValue(sr_cnt, sink.len - sink.width),
NextValue(dq_oe, sink.mask),
sr_out_load.eq(1),
# Start XFER.
NextState("XFER"),
Expand Down Expand Up @@ -214,6 +210,7 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
# Send Data In to Core and return to WAIT when accepted.
source.valid.eq(1),
source.last.eq(1),
NextValue(dq_oe, 0),
If(source.ready,
NextState("WAIT-CMD-DATA"),
)
Expand Down
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