Merge pull request #542 from trabucayre/rm_jtagbone_uartbone

remove jtagbone uartbone

litex_boards/targets/adi_adrv2crr_fmc.py

@@ -71,6 +71,8 @@ def __init__(self, sys_clk_freq=150e6, ddram_channel=0,
         self.crg = CRG(platform, sys_clk_freq, ddram_channel)
 
         # SoCCore ----------------------------------------------------------------------------------
+        kwargs["with_jtagbone"] = True
+
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ADI ADRV2CRR-FMC", **kwargs)
 
         # DDR4 SDRAM -------------------------------------------------------------------------------
@@ -117,9 +119,6 @@ def __init__(self, sys_clk_freq=150e6, ddram_channel=0,
         # SYSMON -----------------------------------------------------------------------------------
         self.sysmon = ZynqUSPSystemMonitor()
 
-        # JTAG -------------------------------------------------------------------------------------
-        self.add_jtagbone()
-
 # Build --------------------------------------------------------------------------------------------
 
 def main():

litex_boards/targets/adi_plutosdr.py

@@ -64,12 +64,10 @@ def __init__(self, sys_clk_freq=100e6, **kwargs):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "crossover"
+        kwargs["uart_name"]     = "crossover"
+        kwargs["with_jtagbone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Pluto SDR", **kwargs)
 
-        # JTAGBone ---------------------------------------------------------------------------------
-        self.add_jtagbone()
-
         # GPIOS ------------------------------------------------------------------------------------
         self.comb += platform.request("gpio", 0).eq(ClockSignal("sys"))
 

litex_boards/targets/analog_pocket.py

@@ -144,9 +144,6 @@ def __init__(self, pads, clock_domain="sys"):
                     # litex_term crossover
                     # litescope_cli -r main_vfb_dma_source_source_last
 
-                    # Add JTAGBone.
-                    self.add_jtagbone()
-
                     # Add UART auto-flush.
                     self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)
 

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -85,8 +85,6 @@ def __init__(self, *, sys_clk_freq=100e6, iodelay_clk_freq=200e6,
             eth_dynamic_ip         = False,
             with_hyperram          = False,
             with_sdcard            = False,
-            with_jtagbone          = True,
-            with_uartbone          = False,
             with_spi_flash         = False,
             with_led_chaser        = True,
             with_video_terminal    = False,
@@ -142,10 +140,6 @@ def __init__(self, *, sys_clk_freq=100e6, iodelay_clk_freq=200e6,
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # UartBone ---------------------------------------------------------------------------------
-        if with_uartbone:
-            self.add_uartbone(baudrate=1e6)
-
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(
@@ -205,8 +199,6 @@ def main():
     parser.add_target_argument("--eth-reset-time",         default="10e-3",        help="Duration of Ethernet PHY reset.")
     parser.add_target_argument("--with-hyperram",          action="store_true",    help="Add HyperRAM.")
     parser.add_target_argument("--with-sdcard",            action="store_true",    help="Add SDCard.")
-    parser.add_target_argument("--with-jtagbone",          action="store_true",    help="Add JTAGBone.")
-    parser.add_target_argument("--with-uartbone",          action="store_true",    help="Add UartBone on 2nd serial.")
     parser.add_target_argument("--with-video-terminal",    action="store_true",    help="Enable Video Terminal (HDMI).")
     parser.add_target_argument("--with-video-framebuffer", action="store_true",    help="Enable Video Framebuffer (HDMI).")
     parser.add_target_argument("--with-spi-flash",         action="store_true",    help="Enable SPI Flash (MMAPed).")
@@ -223,8 +215,6 @@ def main():
         eth_dynamic_ip         = args.eth_dynamic_ip,
         with_hyperram          = args.with_hyperram,
         with_sdcard            = args.with_sdcard,
-        with_jtagbone          = args.with_jtagbone,
-        with_uartbone          = args.with_uartbone,
         with_spi_flash         = args.with_spi_flash,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -55,8 +55,6 @@ def __init__(self, *, sys_clk_freq=50e6, iodelay_clk_freq=200e6,
             eth_dynamic_ip  = False,
             with_hyperram   = False,
             with_sdcard     = False,
-            with_jtagbone   = True,
-            with_uartbone   = False,
             with_led_chaser = True,
             **kwargs):
         platform = antmicro_lpddr4_test_board.Platform()
@@ -104,14 +102,6 @@ def __init__(self, *, sys_clk_freq=50e6, iodelay_clk_freq=200e6,
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
-        # UartBone ---------------------------------------------------------------------------------
-        if with_uartbone:
-            self.add_uartbone(baudrate=1e6)
-
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(
@@ -133,8 +123,6 @@ def main():
     parser.add_target_argument("--eth-dynamic-ip",   action="store_true",    help="Enable dynamic Ethernet IP addresses setting.")
     parser.add_target_argument("--with-hyperram",    action="store_true",    help="Add HyperRAM.")
     parser.add_target_argument("--with-sdcard",      action="store_true",    help="Add SDCard.")
-    parser.add_target_argument("--with-jtagbone",    action="store_true",    help="Add JTAGBone.")
-    parser.add_target_argument("--with-uartbone",    action="store_true",    help="Add UartBone on 2nd serial.")
     args = parser.parse_args()
 
     assert not (args.with_etherbone and args.eth_dynamic_ip)
@@ -148,8 +136,6 @@ def main():
         eth_dynamic_ip    = args.eth_dynamic_ip,
         with_hyperram     = args.with_hyperram,
         with_sdcard       = args.with_sdcard,
-        with_jtagbone     = args.with_jtagbone,
-        with_uartbone     = args.with_uartbone,
         **parser.soc_argdict)
     builder = Builder(soc, **parser.builder_argdict)
     if args.build:

litex_boards/targets/arduino_mkrvidor4000.py

@@ -55,9 +55,9 @@ def __init__(self, sys_clk_freq=48e6, **kwargs):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
+        kwargs["with_jtagbone"] = True # TODO: untested
 
-        self.add_jtagbone() # TODO: untested
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:

litex_boards/targets/colorlight_5a_75x.py

@@ -122,7 +122,6 @@ class BaseSoC(SoCCore):
     def __init__(self, board, revision, sys_clk_freq=60e6, toolchain="trellis",
         with_ethernet    = False,
         with_etherbone   = False,
-        with_uartbone    = False,
         eth_ip           = "192.168.1.50",
         eth_phy          = 0,
         with_led_chaser  = True,
@@ -155,6 +154,11 @@ def __init__(self, board, revision, sys_clk_freq=60e6, toolchain="trellis",
         )
 
         # SoCCore ----------------------------------------------------------------------------------
+        # Uartbone ---------------------------------------------------------------------------------
+        if kwargs["with_uartbone"]:
+            if board != "i5a-907":
+                raise ValueError("uartbone only supported on i5a-907")
+
         SoCCore.__init__(self, platform, int(sys_clk_freq), ident="LiteX SoC on Colorlight " + board.upper(), **kwargs)
 
         # SDR SDRAM --------------------------------------------------------------------------------
@@ -192,12 +196,6 @@ def __init__(self, board, revision, sys_clk_freq=60e6, toolchain="trellis",
                 pads         = platform.request_all("user_led_n"),
                 sys_clk_freq = sys_clk_freq)
 
-        # Uartbone ---------------------------------------------------------------------------------
-        if with_uartbone:
-            if board != "i5a-907":
-                raise ValueError("uartbone only supported on i5a-907")
-            self.add_uartbone(uart_name="uartbone")
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             if board == "i5a-907":
@@ -229,7 +227,6 @@ def main():
     ethopts = parser.target_group.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",           action="store_true",    help="Enable Ethernet support.")
     ethopts.add_argument("--with-etherbone",          action="store_true",    help="Enable Etherbone support.")
-    parser.add_target_argument("--with-uartbone",     action="store_true",    help="Add uartbone on 'FAN OUT' connector.")
     parser.add_target_argument("--eth-ip",            default="192.168.1.50", help="Ethernet/Etherbone IP address.")
     parser.add_target_argument("--eth-phy",           default=0, type=int,    help="Ethernet PHY (0 or 1).")
     parser.add_target_argument("--use-internal-osc",  action="store_true",    help="Use internal oscillator.")
@@ -242,7 +239,6 @@ def main():
         toolchain        = args.toolchain,
         with_ethernet    = args.with_ethernet,
         with_etherbone   = args.with_etherbone,
-        with_uartbone    = args.with_uartbone,
         eth_ip           = args.eth_ip,
         eth_phy          = args.eth_phy,
         use_internal_osc = args.use_internal_osc,

litex_boards/targets/colorlight_i9plus.py

@@ -84,7 +84,6 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6,
         eth_ip          = "192.168.1.50",
         eth_dynamic_ip  = False,
         with_led_chaser = True,
-        with_jtagbone   = True,
         with_spi_flash  = False,
         **kwargs):
         platform = colorlight_i9plus.Platform(toolchain=toolchain)
@@ -127,10 +126,6 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6,
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import MX25L12833F
@@ -160,7 +155,6 @@ def main():
     parser.add_target_argument("--eth-port",       default=0, type=int,       help="Ethernet port to use (0/1)")
     parser.add_target_argument("--eth-ip",         default="192.168.1.50",    help="Ethernet/Etherbone IP address.")
     parser.add_target_argument("--eth-dynamic-ip", action="store_true",       help="Enable dynamic Ethernet IP addresses setting.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true",       help="Enable JTAGbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
     args = parser.parse_args()
 
@@ -176,7 +170,6 @@ def main():
         eth_port       = args.eth_port,
         eth_ip         = args.eth_ip,
         eth_dynamic_ip = args.eth_dynamic_ip,
-        with_jtagbone  = args.with_jtagbone,
         with_spi_flash = args.with_spi_flash,
         **parser.soc_argdict
     )

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -69,12 +69,10 @@ def __init__(self, sys_clk_freq=200e6, with_pcie=False, pcie_lanes=4, **kwargs):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "crossover"
+        kwargs["uart_name"]    = "crossover"
+        kwargs["with_jtabone"] = True
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder", **kwargs)
 
-        # JTAGBone  --------------------------------------------------------------------------------
-        self.add_jtagbone()
-
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.ddrphy = usddrphy.USDDRPHY(

litex_boards/targets/digilent_arty.py

@@ -78,7 +78,6 @@ def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
         eth_ip          = "192.168.1.50",
         eth_dynamic_ip  = False,
         with_led_chaser = True,
-        with_jtagbone   = True,
         with_spi_flash  = False,
         with_buttons    = False,
         with_pmod_gpio  = False,
@@ -123,10 +122,6 @@ def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import S25FL128L
@@ -174,7 +169,6 @@ def main():
     sdopts.add_argument("--with-spi-sdcard",       action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",           action="store_true", help="Enable SDCard support.")
     parser.add_target_argument("--sdcard-adapter",                      help="SDCard PMOD adapter (digilent or numato).")
-    parser.add_target_argument("--with-jtagbone",  action="store_true", help="Enable JTAGbone support.")
     parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
     parser.add_target_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
     args = parser.parse_args()
@@ -191,7 +185,6 @@ def main():
         with_etherbone = args.with_etherbone,
         eth_ip         = args.eth_ip,
         eth_dynamic_ip = args.eth_dynamic_ip,
-        with_jtagbone  = args.with_jtagbone,
         with_spi_flash = args.with_spi_flash,
         with_pmod_gpio = args.with_pmod_gpio,
         **parser.soc_argdict

litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py

@@ -53,7 +53,6 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=200e6,
         with_spi_flash = False,
         with_hyperram  = False,
-        with_jtagbone  = False,
         with_ethernet  = False,
         with_etherbone = False,
         eth_phy        = 0,
@@ -67,10 +66,6 @@ def __init__(self, sys_clk_freq=200e6,
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit", **kwargs)
 
-        # JTAGBone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import W25Q64JW
@@ -122,7 +117,6 @@ def main():
     parser.add_target_argument("--sys-clk-freq",   default=200e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
     parser.add_target_argument("--with-hyperram",  action="store_true",       help="Enable HyperRAM.")
-    parser.add_target_argument("--with-jtagbone",  action="store_true",       help="Enable JTAGbone support.")
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",      action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",          action="store_true", help="Enable SDCard support.")
@@ -137,7 +131,6 @@ def main():
         sys_clk_freq   = args.sys_clk_freq,
         with_spi_flash = args.with_spi_flash,
         with_hyperram  = args.with_hyperram,
-        with_jtagbone  = args.with_jtagbone,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
         eth_ip         = args.eth_ip,

litex_boards/targets/isx_im1283.py

@@ -51,7 +51,7 @@ def __init__(self, platform, sys_clk_freq, with_video_pll=False, pix_clk=25.175e
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, with_jtagbone=True, **kwargs):
+    def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, **kwargs):
         platform = isx_im1283.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -62,10 +62,6 @@ def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, with_jtagbone=True,
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
@@ -90,15 +86,13 @@ def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=isx_im1283.Platform, description="LiteX SoC on iM1283.")
     parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
-    parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
     sdopts = parser.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support.")
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq = args.sys_clk_freq,
-        with_jtagbone = args.with_jtagbone,
         **parser.soc_argdict
     )
     if args.with_spi_sdcard: