Finish tang_mega_138k renaming to tang_mega_138k_pro.

litex-hub · Mar 26, 2024 · 40c7a63 · 40c7a63
1 parent d5038de
commit 40c7a63
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Showing 3 changed files with 5 additions and 328 deletions.
diff --git a/README.md b/README.md
@@ -221,7 +221,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
     ├── sipeed_tang_nano_4k
     ├── sipeed_tang_nano_9k
     ├── sipeed_tang_nano
-    ├── sipeed_tang_mega_138k
+    ├── sipeed_tang_mega_138k_pro
     ├── sipeed_tang_primer_20k
     ├── sipeed_tang_primer_25k
     ├── sipeed_tang_primer

diff --git a/litex_boards/platforms/sipeed_tang_mega_138k.py b/litex_boards/platforms/sipeed_tang_mega_138k.py
diff --git a/litex_boards/targets/sipeed_tang_mega_138k_pro.py b/litex_boards/targets/sipeed_tang_mega_138k_pro.py
@@ -27,7 +27,7 @@
 from litedram.phy import GW5DDRPHY
 from litex.build.io import DDROutput
 
-from litex_boards.platforms import sipeed_tang_mega_138k
+from litex_boards.platforms import sipeed_tang_mega_138k_pro
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -127,7 +127,7 @@ def __init__(self, sys_clk_freq=50e6,
         with_rgb_led        = False,
         with_buttons        = True,
         **kwargs):
-        platform = sipeed_tang_mega_138k.Platform(toolchain="gowin")
+        platform = sipeed_tang_mega_138k_pro.Platform(toolchain="gowin")
 
         # CRG --------------------------------------------------------------------------------------
         cpu_clk_freq = int(800e6) if kwargs["cpu_type"] == "gowin_ae350" else 0
@@ -137,7 +137,7 @@ def __init__(self, sys_clk_freq=50e6,
             with_video_pll = with_video_terminal,
         )
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs)
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K Pro", **kwargs)
         if cpu_clk_freq:
             self.add_config("CPU_CLK_FREQ", cpu_clk_freq)
 
@@ -222,7 +222,7 @@ def __init__(self, sys_clk_freq=50e6,
 
 def main():
     from litex.build.parser import LiteXArgumentParser
-    parser = LiteXArgumentParser(platform=sipeed_tang_mega_138k.Platform, description="LiteX SoC on Tang Mega 138K.")
+    parser = LiteXArgumentParser(platform=sipeed_tang_mega_138k_pro.Platform, description="LiteX SoC on Tang Mega 138K Pro.")
     parser.add_target_argument("--flash",           action="store_true",      help="Flash Bitstream.")
     parser.add_target_argument("--sys-clk-freq",    default=50e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--with-sdram",      action="store_true",      help="Enable optional SDRAM module.")