sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie ge…

…neration.
litex-hub · May 30, 2023 · 8a263c1 · 8a263c1
1 parent 2ae2dfa
commit 8a263c1
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Showing 2 changed files with 8 additions and 8 deletions.
diff --git a/litex_boards/platforms/sitlinv_stlv7325.py → ...x_boards/platforms/sitlinv_stlv7325_v1.py b/litex_boards/platforms/sitlinv_stlv7325.py → ...x_boards/platforms/sitlinv_stlv7325_v1.py
@@ -15,7 +15,7 @@
 
 def _get_io(voltage="2.5V"):
     assert voltage in ["2.5V", "3.3V"]
-    VCCIO = str(25 if voltage == "2.5V" else 33)
+    VCCIO = {"2.5V": "25", "3.3V": "33"}[voltage]
     _io = [
         # Clk / Rst
         ("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
@@ -203,7 +203,7 @@ def _get_io(voltage="2.5V"):
 
         # PCIe
         ("pcie_x1", 0,
-            Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
+            Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
             Subsignal("clk_p", Pins("H6")),
             Subsignal("clk_n", Pins("H5")),
             Subsignal("rx_p",  Pins("B6")),
@@ -212,7 +212,7 @@ def _get_io(voltage="2.5V"):
             Subsignal("tx_n",  Pins("A3"))
         ),
         ("pcie_x2", 0,
-            Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
+            Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
             Subsignal("clk_p", Pins("H6")),
             Subsignal("clk_n", Pins("H5")),
             Subsignal("rx_p",  Pins("B6 C4")),
@@ -221,7 +221,7 @@ def _get_io(voltage="2.5V"):
             Subsignal("tx_n",  Pins("A3 B1"))
         ),
         ("pcie_x4", 0,
-            Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
+            Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
             Subsignal("clk_p", Pins("H6")),
             Subsignal("clk_n", Pins("H5")),
             Subsignal("rx_p",  Pins("B6 C4 E4 G4")),

diff --git a/litex_boards/targets/sitlinv_stlv7325.py → litex_boards/targets/sitlinv_stlv7325_v1.py b/litex_boards/targets/sitlinv_stlv7325.py → litex_boards/targets/sitlinv_stlv7325_v1.py
@@ -15,7 +15,7 @@
 
 from litex.gen import *
 
-from litex_boards.platforms import sitlinv_stlv7325
+from litex_boards.platforms import sitlinv_stlv7325_v1
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
@@ -85,13 +85,13 @@ def __init__(self, sys_clk_freq=100e6,
         with_video_framebuffer = False,
         with_video_terminal    = False,
         **kwargs):
-        platform = sitlinv_stlv7325.Platform(vccio)
+        platform = sitlinv_stlv7325_v1.Platform(vccio)
 
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325", **kwargs)
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325-V1", **kwargs)
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
@@ -188,7 +188,7 @@ def __init__(self, sys_clk_freq=100e6,
 
 def main():
     from litex.build.parser import LiteXArgumentParser
-    parser = LiteXArgumentParser(platform=sitlinv_stlv7325.Platform, description="LiteX SoC on AliExpress STLV7325.")
+    parser = LiteXArgumentParser(platform=sitlinv_stlv7325_v1.Platform, description="LiteX SoC on Sitlinv STLV7325-V1.")
     parser.add_target_argument("--sys-clk-freq",  default=100e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--vccio",         default="2.5V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
     ethopts = parser.target_group.add_mutually_exclusive_group()