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targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
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to do a reset on the trion t20 a pulse is needed.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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maass-hamburg committed Jun 21, 2024
1 parent 95f5e03 commit 8a33a49
Showing 1 changed file with 9 additions and 1 deletion.
10 changes: 9 additions & 1 deletion litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser

from litex.gen.genlib.misc import WaitTimer

from litedram.modules import NDS36PT5
from litedram.phy import GENSDRPHY

Expand All @@ -40,9 +42,15 @@ def __init__(self, platform, sys_clk_freq):
clk50 = platform.request("clk50")
rst_n = platform.request("user_btn", 0)

# A pulse is necessary to do a reset.
self.rst_pulse = Signal()
reset_timer = WaitTimer(1e6)
self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done)
self.comb += reset_timer.wait.eq(self.rst)

# PLL.
self.pll = pll = TRIONPLL(platform)
self.comb += pll.reset.eq(~rst_n | self.rst)
self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name="sdram_clk")
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