targets/xilinx_zc706: typo...

litex-hub · Mar 29, 2024 · a72f2a2 · a72f2a2
1 parent 27dce96
commit a72f2a2
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/litex_boards/targets/xilinx_zc706.py b/litex_boards/targets/xilinx_zc706.py
@@ -93,7 +93,7 @@ def __init__(self, sys_clk_freq=125e6,
 
         # When nor jtagbone, nor etherbone are set forces jtagbone.
         kwargs["uart_name"]     = "crossover"
-        if kwargs["with_jtagbone"] or with_etherbone:
+        if not (kwargs["with_jtagbone"] or with_etherbone):
             kwargs["with_jtagbone"] = True
 
         # CRG --------------------------------------------------------------------------------------