plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required …

…to have access to the flash), added default clk period constraints
litex-hub · Jul 22, 2024 · ab73201 · ab73201
1 parent 5d4ebeb
commit ab73201
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Showing 3 changed files with 18 additions and 3 deletions.
diff --git a/litex_boards/platforms/lattice_certuspro_nx_evn.py b/litex_boards/platforms/lattice_certuspro_nx_evn.py
@@ -137,9 +137,14 @@ class Platform(LatticeNexusPlatform):
     def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
         assert device in ["LFCPNX"]
         LatticeNexusPlatform.__init__(self, device + "-100-9LFG672C", _io, _connectors, toolchain=toolchain, **kwargs)
-        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
+        # SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
+        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
         # Evaluation mode (with free license)
         self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
 
     def create_programmer(self):
         return OpenFPGALoader()
+
+    def do_finalize(self, fragment):
+        LatticeNexusPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
diff --git a/litex_boards/platforms/lattice_certuspro_nx_versa.py b/litex_boards/platforms/lattice_certuspro_nx_versa.py
@@ -136,9 +136,14 @@ class Platform(LatticeNexusPlatform):
     def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
         assert device in ["LFCPNX"]
         LatticeNexusPlatform.__init__(self, device + "-100-9LFG672I", _io, _connectors, toolchain=toolchain, **kwargs)
-        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
+        # SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
+        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
         # Evaluation mode (with free license)
         self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
 
     def create_programmer(self):
         return OpenFPGALoader()
+
+    def do_finalize(self, fragment):
+        LatticeNexusPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clkin125", loose=True), 1e9/125e6)
diff --git a/litex_boards/platforms/lattice_certuspro_nx_vvml.py b/litex_boards/platforms/lattice_certuspro_nx_vvml.py
@@ -110,9 +110,14 @@ class Platform(LatticeNexusPlatform):
     def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
         assert device in ["LFCPNX"]
         LatticeNexusPlatform.__init__(self, device + "-100-9BBG484I", _io, _connectors, toolchain=toolchain, **kwargs)
-        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
+        # SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
+        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
         # Evaluation mode (with free license)
         self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
 
     def create_programmer(self):
         return OpenFPGALoader()
+
+    def do_finalize(self, fragment):
+        LatticeNexusPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)