targets/CRG: Add rst signal when missing.

Allow properly reseting the PLL from the SoC.
litex-hub · Jul 26, 2023 · c1088be · c1088be
1 parent ace7896
commit c1088be
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Showing 18 changed files with 37 additions and 12 deletions.
diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@@ -39,6 +39,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq, iodelay_clk_freq, with_video_pll=False):
+        self.rst          = Signal()
         self.cd_sys       = ClockDomain()
         self.cd_sys2x     = ClockDomain()
         self.cd_sys4x     = ClockDomain()
@@ -54,6 +55,7 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq, with_video_pll=Fals
         clk100 = platform.request("clk100")
 
         self.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys2x,     2 * sys_clk_freq)
@@ -66,6 +68,7 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq, with_video_pll=Fals
         # Video PLL.
         if with_video_pll:
             self.video_pll = video_pll = S7MMCM(speedgrade=-1)
+            self.comb += video_pll.reset.eq(self.rst)
             video_pll.register_clkin(clk100, 100e6)
             video_pll.create_clkout(self.cd_hdmi,   40e6)
             video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)

diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py
@@ -27,6 +27,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
+        self.rst       = Signal()
         self.cd_sys    = ClockDomain()
         self.cd_sys2x  = ClockDomain()
         self.cd_sys8x  = ClockDomain()
@@ -35,6 +36,7 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
         # # #
 
         self.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys2x,  2 * sys_clk_freq)

diff --git a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py
@@ -32,6 +32,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_por = ClockDomain()
         self.cd_sys = ClockDomain()
 
@@ -48,6 +49,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL
         self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
+        self.comb += sys_pll.reset.eq(self.rst)
         sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
         sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done)

diff --git a/litex_boards/targets/decklink_intensity_pro_4k.py b/litex_boards/targets/decklink_intensity_pro_4k.py
@@ -28,12 +28,13 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
 
         self.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(ResetSignal("pcie"))
+        self.comb += pll.reset.eq(ResetSignal("pcie") | self.rst)
         pll.register_clkin(ClockSignal("pcie"), 125e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.

diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py
@@ -36,6 +36,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst       = Signal()
         self.cd_sys    = ClockDomain()
         self.cd_sys4x  = ClockDomain()
         self.cd_pll4x  = ClockDomain()
@@ -44,6 +45,7 @@ def __init__(self, platform, sys_clk_freq):
         # # #
 
         self.pll = pll = USMMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 200e6)

diff --git a/litex_boards/targets/efinix_t8f81_dev_kit.py b/litex_boards/targets/efinix_t8f81_dev_kit.py
@@ -29,6 +29,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -38,7 +39,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL.
         self.pll = pll = TRIONPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk33, 33.333e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
 

diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
@@ -28,6 +28,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -37,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL
         self.pll = pll = TITANIUMPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk25, 25e6)
         # You can use CLKOUT0 only for clocks with a maximum frequency of 4x
         # (integer) of the reference clock. If all your system clocks do not fall within

diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
@@ -27,6 +27,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -37,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL
         self.pll = pll = TRIONPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk40, 40e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk")
 

diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
@@ -26,6 +26,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -35,7 +36,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL
         self.pll = pll = TRIONPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
 

diff --git a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py
@@ -24,6 +24,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -33,7 +34,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL
         self.pll = pll = TRIONPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
 

diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py
@@ -28,6 +28,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -37,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL.
         self.pll = pll = TRIONPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk33, 33.333e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
 

diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py
@@ -45,6 +45,7 @@
 
 class CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq, with_pcie=False):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -57,6 +58,7 @@ def __init__(self, platform, sys_clk_freq, with_pcie=False):
             ]
         else:
             self.pll = pll = S7PLL(speedgrade=-2)
+            self.comb += pll.reset.eq(self.rst)
             pll.register_clkin(platform.request("clk60"), 60e6)
             pll.create_clkout(self.cd_sys, sys_clk_freq)
 

diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py
@@ -32,6 +32,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_sys = ClockDomain()
 
         # # #
@@ -41,7 +42,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL.
         self.pll = pll = TRIONPLL(platform)
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk33, 33.333e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
 

diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py
@@ -32,6 +32,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
         self.cd_por = ClockDomain()
         self.cd_sys = ClockDomain()
 
@@ -51,6 +52,7 @@ def __init__(self, platform, sys_clk_freq):
 
         # PLL
         self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
+        self.comb += sys_pll.reset.eq(self.rst)
         sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
         sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done )

diff --git a/litex_boards/targets/sipeed_tang_primer.py b/litex_boards/targets/sipeed_tang_primer.py
@@ -25,7 +25,8 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.cd_sys   = ClockDomain()
+        self.rst    = Signal()
+        self.cd_sys = ClockDomain()
 
         # # #
 
@@ -34,7 +35,7 @@ def __init__(self, platform, sys_clk_freq):
         rst_n = platform.request("user_btn", 0)
 
         self.comb += self.cd_sys.clk.eq(clk24)
-        self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n | self.rst)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 

diff --git a/litex_boards/targets/sipeed_tang_primer_20k.py b/litex_boards/targets/sipeed_tang_primer_20k.py
@@ -56,7 +56,7 @@ def __init__(self, platform, sys_clk_freq, with_video_pll=False):
 
         # PLL
         self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
-        self.comb += pll.reset.eq(~por_done)
+        self.comb += pll.reset.eq(~por_done | self.rst)
         pll.register_clkin(clk27, 27e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         self.specials += [

diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py
@@ -46,6 +46,7 @@
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq, ddram_channel, with_hbm):
         if with_hbm:
+            self.rst        = Signal()
             self.cd_sys     = ClockDomain()
             self.cd_hbm_ref = ClockDomain()
             self.cd_apb     = ClockDomain()
@@ -60,6 +61,7 @@ def __init__(self, platform, sys_clk_freq, ddram_channel, with_hbm):
 
         if with_hbm:
             self.pll = pll = USMMCM(speedgrade=-2)
+            self.comb += pll.reset.eq(self.rst)
             pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
             pll.create_clkout(self.cd_sys,     sys_clk_freq)
             pll.create_clkout(self.cd_hbm_ref, 100e6)

diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py
@@ -31,6 +31,7 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
+        self.rst          = Signal()
         self.cd_sys       = ClockDomain()
         self.cd_sys4x     = ClockDomain()
         self.cd_sys4x_dqs = ClockDomain()
@@ -53,7 +54,7 @@ def __init__(self, platform, sys_clk_freq):
         self.comb += self.cd_por.clk.eq(clk48)
         self.comb += por_done.eq(por_count == 0)
         self.sync.por += If(~por_done, por_count.eq(por_count - 1))
-        self.comb += pll.reset.eq(~por_done)
+        self.comb += pll.reset.eq(~por_done | self.rst)
 
         self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)