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[RISCV] Enable load clustering by default
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@asb
asb committed Dec 13, 2023
1 parent ef43091 commit 1a46b84
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Showing 50 changed files with 9,657 additions and 9,629 deletions.
16 changes: 3 additions & 13 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -95,11 +95,6 @@ static cl::opt<bool>
cl::desc("Enable Split RegisterAlloc for RVV"),
cl::init(true));

static cl::opt<bool> EnableMISchedLoadClustering(
"riscv-misched-load-clustering", cl::Hidden,
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
Expand Down Expand Up @@ -345,15 +340,10 @@ class RISCVPassConfig : public TargetPassConfig {
ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext *C) const override {
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
ScheduleDAGMILive *DAG = nullptr;
if (EnableMISchedLoadClustering) {
DAG = createGenericSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI, true));
}
if (ST.hasMacroFusion()) {
DAG = DAG ? DAG : createGenericSchedLive(C);
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI, true));
if (ST.hasMacroFusion())
DAG->addMutation(createRISCVMacroFusionDAGMutation());
}
return DAG;
}

Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -63,15 +63,15 @@ define i32 @va1(ptr %fmt, ...) {
; RV64-NEXT: sd a2, 32(sp)
; RV64-NEXT: sd a3, 40(sp)
; RV64-NEXT: sd a4, 48(sp)
; RV64-NEXT: sd a5, 56(sp)
; RV64-NEXT: addi a0, sp, 24
; RV64-NEXT: sd a0, 8(sp)
; RV64-NEXT: lw a0, 12(sp)
; RV64-NEXT: lwu a1, 8(sp)
; RV64-NEXT: lwu a0, 8(sp)
; RV64-NEXT: lw a1, 12(sp)
; RV64-NEXT: sd a5, 56(sp)
; RV64-NEXT: sd a6, 64(sp)
; RV64-NEXT: sd a7, 72(sp)
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: addi a1, a0, 4
; RV64-NEXT: srli a2, a1, 32
; RV64-NEXT: sw a1, 8(sp)
Expand Down Expand Up @@ -968,22 +968,22 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: sd a4, 304(a0)
; RV64-NEXT: lui a0, 24414
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: sd a5, 312(a0)
; RV64-NEXT: lui a0, 24414
; RV64-NEXT: addiw a0, a0, 280
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: sd a0, 8(sp)
; RV64-NEXT: lw a0, 12(sp)
; RV64-NEXT: lwu a1, 8(sp)
; RV64-NEXT: lwu a0, 8(sp)
; RV64-NEXT: lw a1, 12(sp)
; RV64-NEXT: lui a2, 24414
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a5, 312(a2)
; RV64-NEXT: lui a2, 24414
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a6, 320(a2)
; RV64-NEXT: lui a2, 24414
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a7, 328(a2)
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: addi a1, a0, 4
; RV64-NEXT: srli a2, a1, 32
; RV64-NEXT: sw a1, 8(sp)
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/RISCV/add-before-shl.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -167,17 +167,17 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: srli a5, a2, 29
; RV32I-NEXT: slli a6, a3, 3
; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: srli a3, a3, 29
; RV32I-NEXT: slli a6, a1, 3
; RV32I-NEXT: slli a6, a4, 3
; RV32I-NEXT: or a3, a6, a3
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: slli a4, a4, 3
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a4, 29
; RV32I-NEXT: slli a1, a1, 3
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: slli a2, a2, 3
; RV32I-NEXT: lui a4, 128
; RV32I-NEXT: add a1, a1, a4
Expand All @@ -200,26 +200,26 @@ define i128 @add_wide_operand(i128 %a) nounwind {
;
; RV32C-LABEL: add_wide_operand:
; RV32C: # %bb.0:
; RV32C-NEXT: lw a6, 4(a1)
; RV32C-NEXT: c.lw a3, 12(a1)
; RV32C-NEXT: c.lw a4, 0(a1)
; RV32C-NEXT: c.lw a2, 12(a1)
; RV32C-NEXT: lw a6, 0(a1)
; RV32C-NEXT: c.lw a3, 4(a1)
; RV32C-NEXT: c.lw a1, 8(a1)
; RV32C-NEXT: c.lui a5, 16
; RV32C-NEXT: c.add a3, a5
; RV32C-NEXT: c.slli a3, 3
; RV32C-NEXT: c.add a2, a5
; RV32C-NEXT: c.slli a2, 3
; RV32C-NEXT: srli a5, a1, 29
; RV32C-NEXT: c.or a3, a5
; RV32C-NEXT: srli a5, a4, 29
; RV32C-NEXT: slli a2, a6, 3
; RV32C-NEXT: c.or a2, a5
; RV32C-NEXT: srli a5, a6, 29
; RV32C-NEXT: slli a4, a3, 3
; RV32C-NEXT: c.or a4, a5
; RV32C-NEXT: c.srli a3, 29
; RV32C-NEXT: c.slli a1, 3
; RV32C-NEXT: c.or a1, a5
; RV32C-NEXT: c.slli a4, 3
; RV32C-NEXT: c.sw a4, 0(a0)
; RV32C-NEXT: c.or a1, a3
; RV32C-NEXT: c.slli a6, 3
; RV32C-NEXT: sw a6, 0(a0)
; RV32C-NEXT: c.sw a1, 8(a0)
; RV32C-NEXT: c.sw a2, 4(a0)
; RV32C-NEXT: c.sw a3, 12(a0)
; RV32C-NEXT: c.sw a4, 4(a0)
; RV32C-NEXT: c.sw a2, 12(a0)
; RV32C-NEXT: c.jr ra
;
; RV64C-LABEL: add_wide_operand:
Expand Down
104 changes: 52 additions & 52 deletions llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -192,37 +192,37 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a4, 4(a0)
; RV32-NEXT: lw a5, 0(a0)
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s1, a2
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB11_2
; RV32-NEXT: .LBB11_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32-NEXT: sw a5, 8(sp)
; RV32-NEXT: sw a4, 12(sp)
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8@plt
; RV32-NEXT: lw a4, 12(sp)
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a4, 8(sp)
; RV32-NEXT: lw a5, 12(sp)
; RV32-NEXT: bnez a0, .LBB11_6
; RV32-NEXT: .LBB11_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: beq a4, s1, .LBB11_4
; RV32-NEXT: beq a5, s1, .LBB11_4
; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32-NEXT: slt a0, s1, a4
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: slt a0, s1, a5
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: bnez a0, .LBB11_1
; RV32-NEXT: j .LBB11_5
; RV32-NEXT: .LBB11_4: # in Loop: Header=BB11_2 Depth=1
; RV32-NEXT: sltu a0, s2, a5
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: sltu a0, s2, a4
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: bnez a0, .LBB11_1
; RV32-NEXT: .LBB11_5: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
Expand Down Expand Up @@ -268,37 +268,37 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a4, 4(a0)
; RV32-NEXT: lw a5, 0(a0)
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s1, a2
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB13_2
; RV32-NEXT: .LBB13_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32-NEXT: sw a5, 8(sp)
; RV32-NEXT: sw a4, 12(sp)
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8@plt
; RV32-NEXT: lw a4, 12(sp)
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a4, 8(sp)
; RV32-NEXT: lw a5, 12(sp)
; RV32-NEXT: bnez a0, .LBB13_6
; RV32-NEXT: .LBB13_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: beq a4, s1, .LBB13_4
; RV32-NEXT: beq a5, s1, .LBB13_4
; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32-NEXT: sltu a0, s1, a4
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: sltu a0, s1, a5
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: bnez a0, .LBB13_1
; RV32-NEXT: j .LBB13_5
; RV32-NEXT: .LBB13_4: # in Loop: Header=BB13_2 Depth=1
; RV32-NEXT: sltu a0, s2, a5
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: sltu a0, s2, a4
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: bnez a0, .LBB13_1
; RV32-NEXT: .LBB13_5: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
Expand Down Expand Up @@ -344,37 +344,37 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a4, 4(a0)
; RV32-NEXT: lw a5, 0(a0)
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s1, a2
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB15_2
; RV32-NEXT: .LBB15_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
; RV32-NEXT: sw a5, 8(sp)
; RV32-NEXT: sw a4, 12(sp)
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8@plt
; RV32-NEXT: lw a4, 12(sp)
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a4, 8(sp)
; RV32-NEXT: lw a5, 12(sp)
; RV32-NEXT: bnez a0, .LBB15_6
; RV32-NEXT: .LBB15_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: beq a4, s1, .LBB15_4
; RV32-NEXT: beq a5, s1, .LBB15_4
; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
; RV32-NEXT: slt a0, s1, a4
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: slt a0, s1, a5
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: beqz a0, .LBB15_1
; RV32-NEXT: j .LBB15_5
; RV32-NEXT: .LBB15_4: # in Loop: Header=BB15_2 Depth=1
; RV32-NEXT: sltu a0, s2, a5
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: sltu a0, s2, a4
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: beqz a0, .LBB15_1
; RV32-NEXT: .LBB15_5: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
Expand Down Expand Up @@ -420,37 +420,37 @@ define void @amominu_d_discard(ptr %a, i64 %b) nounwind {
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a4, 4(a0)
; RV32-NEXT: lw a5, 0(a0)
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: mv s1, a2
; RV32-NEXT: mv s2, a1
; RV32-NEXT: j .LBB17_2
; RV32-NEXT: .LBB17_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
; RV32-NEXT: sw a5, 8(sp)
; RV32-NEXT: sw a4, 12(sp)
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a5, 12(sp)
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8@plt
; RV32-NEXT: lw a4, 12(sp)
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a4, 8(sp)
; RV32-NEXT: lw a5, 12(sp)
; RV32-NEXT: bnez a0, .LBB17_6
; RV32-NEXT: .LBB17_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: beq a4, s1, .LBB17_4
; RV32-NEXT: beq a5, s1, .LBB17_4
; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
; RV32-NEXT: sltu a0, s1, a4
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: sltu a0, s1, a5
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: beqz a0, .LBB17_1
; RV32-NEXT: j .LBB17_5
; RV32-NEXT: .LBB17_4: # in Loop: Header=BB17_2 Depth=1
; RV32-NEXT: sltu a0, s2, a5
; RV32-NEXT: mv a2, a5
; RV32-NEXT: mv a3, a4
; RV32-NEXT: sltu a0, s2, a4
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a5
; RV32-NEXT: beqz a0, .LBB17_1
; RV32-NEXT: .LBB17_5: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
Expand Down
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