[X86] Fix MSVC implicit shift extension warning.

llvm · Sep 20, 2024 · 3bcffe5 · 3bcffe5
1 parent cee0bf9
commit 3bcffe5
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30007,7 +30007,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
       // This is equal to Masked - 2*SignBitMask which will correctly sign
       // extend our result.
       SDValue CstHighBit =
-          DAG.getConstant(1 << (EltSizeInBits - 1), dl, NarrowScalarVT);
+          DAG.getConstant(1ULL << (EltSizeInBits - 1), dl, NarrowScalarVT);
       SDValue SplatHighBit = DAG.getSplat(VT, dl, CstHighBit);
       // This does not induce recursion, all operands are constants.
       SDValue SignBitMask = DAG.getNode(LogicalOpc, dl, VT, SplatHighBit, Amt);