fix test; remove G_BUILD_VECTOR change

llvm · Nov 7, 2023 · abd6030 · abd6030
1 parent ef140d5
commit abd6030
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1435,7 +1435,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     if (DstTy.getElementType() != SrcEltTy)
       report("G_BUILD_VECTOR result element type must match source type", MI);
 
-    if (DstTy.getElementCount().getKnownMinValue() > MI->getNumOperands() - 1)
+    if (DstTy.getNumElements() != MI->getNumOperands() - 1)
       report("G_BUILD_VECTOR must have an operand for each elemement", MI);
 
     for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \
-; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32,RV32-F16 %s
+; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \
-; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64,RV64-F16 %s
+; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
 
 ; ==========================================================================
 ; ============================= Scalable Types =============================