[X86] Add MMX nontemporal store DAG test

As noticed on #98505 - we had fast-isel test but not SDAG
llvm · Jul 23, 2024 · b97bc56 · b97bc56
1 parent ec56790
commit b97bc56
Showing 1 changed file with 28 additions and 4 deletions.
diff --git a/llvm/test/CodeGen/X86/nontemporal.ll b/llvm/test/CodeGen/X86/nontemporal.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+avx | FileCheck %s --check-prefixes=X86,X86-AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=X64,X64-SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx | FileCheck %s --check-prefixes=X64,X64-AVX
 
 define i32 @f(<4 x float> %A, ptr %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4 x i32> %F, <8 x i16> %G, <16 x i8> %H, i64 %I, ptr %loadptr) nounwind {
 ; X86-SSE-LABEL: f:
@@ -176,4 +176,28 @@ define i32 @f(<4 x float> %A, ptr %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4
   ret i32 %sum8
 }
 
+define void @test_mmx(ptr nocapture %a0, ptr nocapture %a1) {
+; X86-LABEL: test_mmx:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    movq (%ecx), %mm0
+; X86-NEXT:    psrlq $3, %mm0
+; X86-NEXT:    movq %mm0, (%eax)
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_mmx:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movq (%rdi), %mm0
+; X64-NEXT:    psrlq $3, %mm0
+; X64-NEXT:    movq %mm0, (%rsi)
+; X64-NEXT:    retq
+entry:
+  %0 = load x86_mmx, ptr %a0
+  %1 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %0, i32 3)
+  store x86_mmx %1, ptr %a1, align 8, !nontemporal !0
+  ret void
+}
+declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
+
 !0 = !{i32 1}