fixup! [RISCV] RISCV vector calling convention (2/2)

llvm · Feb 26, 2024 · db17c2b · db17c2b
1 parent 3cb56d3
commit db17c2b
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Showing 3 changed files with 27 additions and 26 deletions.
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -521,7 +521,7 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   CallingConv::ID CC = F.getCallingConv();
 
   SmallVector<ArgInfo, 32> SplitArgInfos;
-  std::vector<Type *> TypeList;
+  SmallVector<Type *, 4> TypeList;
   unsigned Index = 0;
   for (auto &Arg : F.args()) {
     // Construct the ArgInfo object from destination register and argument type.
@@ -579,7 +579,7 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 
   SmallVector<ArgInfo, 32> SplitArgInfos;
   SmallVector<ISD::OutputArg, 8> Outs;
-  std::vector<Type *> TypeList;
+  SmallVector<Type *, 4> TypeList;
   for (auto &AInfo : Info.OrigArgs) {
     // Handle any required unmerging of split value types from a given VReg into
     // physical registers. ArgInfo objects are constructed correspondingly and

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18032,7 +18032,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   }
 
   // Allocate to a register if possible, or else a stack slot.
-  Register Reg = MCRegister();
+  Register Reg;
   unsigned StoreSizeBytes = XLen / 8;
   Align StackAlign = Align(XLen / 8);
 
@@ -18129,7 +18129,7 @@ void RISCVTargetLowering::analyzeInputArgs(
   unsigned NumArgs = Ins.size();
   FunctionType *FType = MF.getFunction().getFunctionType();
 
-  std::vector<Type *> TypeList;
+  SmallVector<Type *, 4> TypeList;
   if (IsRet)
     TypeList.push_back(MF.getFunction().getReturnType());
   else
@@ -18164,7 +18164,7 @@ void RISCVTargetLowering::analyzeOutputArgs(
     CallLoweringInfo *CLI, RISCVCCAssignFn Fn) const {
   unsigned NumArgs = Outs.size();
 
-  std::vector<Type *> TypeList;
+  SmallVector<Type *, 4> TypeList;
   if (IsRet)
     TypeList.push_back(MF.getFunction().getReturnType());
   else if (CLI)
@@ -19073,8 +19073,7 @@ bool RISCVTargetLowering::CanLowerReturn(
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 
-  std::vector<Type *> TypeList = {MF.getFunction().getReturnType()};
-  RVVArgDispatcher Dispatcher{&MF, this, TypeList};
+  RVVArgDispatcher Dispatcher{&MF, this, MF.getFunction().getReturnType()};
 
   for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
     MVT VT = Outs[i].VT;
@@ -20877,7 +20876,7 @@ unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
   return Subtarget.getMinimumJumpTableEntries();
 }
 
-void RVVArgDispatcher::constructArgInfos(Type *Ty) {
+void RVVArgDispatcher::constructArgInfos(Type *Ty, bool &FirstMaskAssigned) {
   const DataLayout &DL = MF->getDataLayout();
   const Function &F = MF->getFunction();
   LLVMContext &Context = F.getContext();
@@ -20909,21 +20908,23 @@ void RVVArgDispatcher::constructArgInfos(Type *Ty) {
       if (RegisterVT.isFixedLengthVector())
         RegisterVT = TLI->getContainerForFixedLengthVector(RegisterVT);
 
-      RVVArgInfo Info{1, RegisterVT, false};
-      RVVArgInfos.insert(RVVArgInfos.end(), NumRegs, Info);
+      if (!FirstMaskAssigned && RegisterVT.getVectorElementType() == MVT::i1) {
+        RVVArgInfos.push_back({1, RegisterVT, true});
+        FirstMaskAssigned = true;
+      } else {
+        RVVArgInfos.push_back({1, RegisterVT, false});
+      }
+
+      RVVArgInfos.insert(RVVArgInfos.end(), --NumRegs, {1, RegisterVT, false});
     }
   }
 }
 
-void RVVArgDispatcher::construct(const std::vector<Type *> &TypeList) {
+void RVVArgDispatcher::constructArgInfos(
+    const SmallVectorImpl<Type *> &TypeList) {
+  bool FirstVMaskAssigned = false;
   for (Type *Ty : TypeList)
-    constructArgInfos(Ty);
-
-  for (auto &Info : RVVArgInfos)
-    if (Info.NF == 1 && Info.VT.getVectorElementType() == MVT::i1) {
-      Info.FirstVMask = true;
-      break;
-    }
+    constructArgInfos(Ty, FirstVMaskAssigned);
 }
 
 void RVVArgDispatcher::allocatePhysReg(unsigned NF, unsigned LMul,

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -1038,33 +1038,33 @@ class RVVArgDispatcher {
   };
 
   RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI,
-                   std::vector<Type *> &TypeList)
+                   SmallVectorImpl<Type *> &TypeList)
       : MF(MF), TLI(TLI) {
-    construct(TypeList);
+    constructArgInfos(TypeList);
     compute();
   }
 
   RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI,
                    Type *Ty)
       : MF(MF), TLI(TLI) {
-    std::vector<Type *> TypeList = {Ty};
-    construct(TypeList);
+    SmallVector<Type *, 4> TypeList = {Ty};
+    constructArgInfos(TypeList);
     compute();
   }
 
   MCPhysReg getNextPhysReg();
 
 private:
-  std::vector<RVVArgInfo> RVVArgInfos;
-  std::vector<MCPhysReg> AllocatedPhysRegs;
+  SmallVector<RVVArgInfo, 4> RVVArgInfos;
+  SmallVector<MCPhysReg, 4> AllocatedPhysRegs;
 
   const MachineFunction *MF = nullptr;
   const RISCVTargetLowering *TLI = nullptr;
 
   unsigned CurIdx = 0;
 
-  void construct(const std::vector<Type *> &TypeList);
-  void constructArgInfos(Type *Ty);
+  void constructArgInfos(const SmallVectorImpl<Type *> &TypeList);
+  void constructArgInfos(Type *Ty, bool &FirstMaskAssigned);
   void compute();
   void allocatePhysReg(unsigned NF = 1, unsigned LMul = 1,
                        unsigned StartReg = 0);