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[RISCV] Enable store clustering by default
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@asb
asb committed Nov 29, 2023
1 parent 7a50880 commit e2742f4
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Showing 37 changed files with 2,056 additions and 2,071 deletions.
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -347,6 +347,7 @@ class RISCVPassConfig : public TargetPassConfig {
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
if (ST.hasMacroFusion())
DAG->addMutation(createRISCVMacroFusionDAGMutation());
return DAG;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/add-before-shl.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -182,8 +182,8 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32I-NEXT: lui a4, 128
; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: jalr zero, 0(ra)
;
Expand Down Expand Up @@ -217,8 +217,8 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32C-NEXT: or a2, a6, a2
; RV32C-NEXT: c.slli a1, 3
; RV32C-NEXT: c.sw a1, 0(a0)
; RV32C-NEXT: c.sw a2, 8(a0)
; RV32C-NEXT: c.sw a4, 4(a0)
; RV32C-NEXT: c.sw a2, 8(a0)
; RV32C-NEXT: c.sw a3, 12(a0)
; RV32C-NEXT: c.jr ra
;
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/alloca.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -76,21 +76,21 @@ define void @alloca_callframe(i32 %n) nounwind {
; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: li a1, 10
; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: li t0, 9
; RV32I-NEXT: li t0, 12
; RV32I-NEXT: li t1, 11
; RV32I-NEXT: li t2, 10
; RV32I-NEXT: li t3, 9
; RV32I-NEXT: li a1, 2
; RV32I-NEXT: li a2, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 5
; RV32I-NEXT: li a5, 6
; RV32I-NEXT: li a6, 7
; RV32I-NEXT: li a7, 8
; RV32I-NEXT: sw t0, 0(sp)
; RV32I-NEXT: sw t0, 12(sp)
; RV32I-NEXT: sw t1, 8(sp)
; RV32I-NEXT: sw t2, 4(sp)
; RV32I-NEXT: sw t3, 0(sp)
; RV32I-NEXT: call func@plt
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, s0, -16
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -146,19 +146,19 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a0, 18
; RV32I-FPELIM-NEXT: li a1, 17
; RV32I-FPELIM-NEXT: li a2, 16
; RV32I-FPELIM-NEXT: lui a3, 262236
; RV32I-FPELIM-NEXT: addi a3, a3, 655
; RV32I-FPELIM-NEXT: lui a4, 377487
; RV32I-FPELIM-NEXT: addi a4, a4, 1475
; RV32I-FPELIM-NEXT: li a5, 15
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: li a0, 17
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: li a0, 16
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: lui a0, 262236
; RV32I-FPELIM-NEXT: addi a0, a0, 655
; RV32I-FPELIM-NEXT: sw a0, 12(sp)
; RV32I-FPELIM-NEXT: lui a0, 377487
; RV32I-FPELIM-NEXT: addi a0, a0, 1475
; RV32I-FPELIM-NEXT: sw a0, 8(sp)
; RV32I-FPELIM-NEXT: li a0, 15
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
; RV32I-FPELIM-NEXT: sw a2, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
; RV32I-FPELIM-NEXT: sw a4, 8(sp)
; RV32I-FPELIM-NEXT: sw a5, 0(sp)
; RV32I-FPELIM-NEXT: lui a0, 262153
; RV32I-FPELIM-NEXT: addi a0, a0, 491
; RV32I-FPELIM-NEXT: sw a0, 44(sp)
Expand Down Expand Up @@ -192,19 +192,19 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: li a0, 18
; RV32I-WITHFP-NEXT: li a1, 17
; RV32I-WITHFP-NEXT: li a2, 16
; RV32I-WITHFP-NEXT: lui a3, 262236
; RV32I-WITHFP-NEXT: addi a3, a3, 655
; RV32I-WITHFP-NEXT: lui a4, 377487
; RV32I-WITHFP-NEXT: addi a4, a4, 1475
; RV32I-WITHFP-NEXT: li a5, 15
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
; RV32I-WITHFP-NEXT: li a0, 17
; RV32I-WITHFP-NEXT: sw a0, 20(sp)
; RV32I-WITHFP-NEXT: li a0, 16
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
; RV32I-WITHFP-NEXT: lui a0, 262236
; RV32I-WITHFP-NEXT: addi a0, a0, 655
; RV32I-WITHFP-NEXT: sw a0, 12(sp)
; RV32I-WITHFP-NEXT: lui a0, 377487
; RV32I-WITHFP-NEXT: addi a0, a0, 1475
; RV32I-WITHFP-NEXT: sw a0, 8(sp)
; RV32I-WITHFP-NEXT: li a0, 15
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: sw a1, 20(sp)
; RV32I-WITHFP-NEXT: sw a2, 16(sp)
; RV32I-WITHFP-NEXT: sw a3, 12(sp)
; RV32I-WITHFP-NEXT: sw a4, 8(sp)
; RV32I-WITHFP-NEXT: sw a5, 0(sp)
; RV32I-WITHFP-NEXT: lui a0, 262153
; RV32I-WITHFP-NEXT: addi a0, a0, 491
; RV32I-WITHFP-NEXT: sw a0, -20(s0)
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -142,15 +142,15 @@ define i32 @caller_many_scalars() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a0, 8
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: li a4, 8
; RV32I-FPELIM-NEXT: li a0, 1
; RV32I-FPELIM-NEXT: li a1, 2
; RV32I-FPELIM-NEXT: li a2, 3
; RV32I-FPELIM-NEXT: li a3, 4
; RV32I-FPELIM-NEXT: li a5, 5
; RV32I-FPELIM-NEXT: li a6, 6
; RV32I-FPELIM-NEXT: li a7, 7
; RV32I-FPELIM-NEXT: sw a4, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: li a4, 0
; RV32I-FPELIM-NEXT: call callee_many_scalars@plt
Expand All @@ -164,15 +164,15 @@ define i32 @caller_many_scalars() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: li a0, 8
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: li a4, 8
; RV32I-WITHFP-NEXT: li a0, 1
; RV32I-WITHFP-NEXT: li a1, 2
; RV32I-WITHFP-NEXT: li a2, 3
; RV32I-WITHFP-NEXT: li a3, 4
; RV32I-WITHFP-NEXT: li a5, 5
; RV32I-WITHFP-NEXT: li a6, 6
; RV32I-WITHFP-NEXT: li a7, 7
; RV32I-WITHFP-NEXT: sw a4, 4(sp)
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
; RV32I-WITHFP-NEXT: li a4, 0
; RV32I-WITHFP-NEXT: call callee_many_scalars@plt
Expand Down Expand Up @@ -354,9 +354,9 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, sp, 16
; RV32I-FPELIM-NEXT: li a1, 9
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: li a0, 9
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 28(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
Expand Down Expand Up @@ -387,9 +387,9 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, s0, -48
; RV32I-WITHFP-NEXT: li a1, 9
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: li a0, 9
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: sw a1, 0(sp)
; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
Expand Down Expand Up @@ -665,16 +665,16 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a0, 19
; RV32I-FPELIM-NEXT: li a1, 18
; RV32I-FPELIM-NEXT: li a2, 17
; RV32I-FPELIM-NEXT: li a3, 16
; RV32I-FPELIM-NEXT: li a4, 15
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: li a0, 18
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: li a0, 17
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
; RV32I-FPELIM-NEXT: sw a2, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: li a0, 16
; RV32I-FPELIM-NEXT: sw a0, 8(sp)
; RV32I-FPELIM-NEXT: li a0, 15
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: sw a3, 8(sp)
; RV32I-FPELIM-NEXT: sw a4, 0(sp)
; RV32I-FPELIM-NEXT: lui a0, 262153
; RV32I-FPELIM-NEXT: addi a0, a0, 491
; RV32I-FPELIM-NEXT: sw a0, 44(sp)
Expand Down Expand Up @@ -708,16 +708,16 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: li a0, 19
; RV32I-WITHFP-NEXT: li a1, 18
; RV32I-WITHFP-NEXT: li a2, 17
; RV32I-WITHFP-NEXT: li a3, 16
; RV32I-WITHFP-NEXT: li a4, 15
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
; RV32I-WITHFP-NEXT: li a0, 18
; RV32I-WITHFP-NEXT: sw a0, 20(sp)
; RV32I-WITHFP-NEXT: li a0, 17
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
; RV32I-WITHFP-NEXT: sw a1, 20(sp)
; RV32I-WITHFP-NEXT: sw a2, 16(sp)
; RV32I-WITHFP-NEXT: sw zero, 12(sp)
; RV32I-WITHFP-NEXT: li a0, 16
; RV32I-WITHFP-NEXT: sw a0, 8(sp)
; RV32I-WITHFP-NEXT: li a0, 15
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: sw a3, 8(sp)
; RV32I-WITHFP-NEXT: sw a4, 0(sp)
; RV32I-WITHFP-NEXT: lui a0, 262153
; RV32I-WITHFP-NEXT: addi a0, a0, 491
; RV32I-WITHFP-NEXT: sw a0, -20(s0)
Expand Down Expand Up @@ -938,13 +938,13 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
; RV32I-FPELIM-LABEL: callee_large_struct_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: li a1, 1
; RV32I-FPELIM-NEXT: li a2, 2
; RV32I-FPELIM-NEXT: li a3, 3
; RV32I-FPELIM-NEXT: li a4, 4
; RV32I-FPELIM-NEXT: sw a1, 0(a0)
; RV32I-FPELIM-NEXT: li a1, 2
; RV32I-FPELIM-NEXT: sw a1, 4(a0)
; RV32I-FPELIM-NEXT: li a1, 3
; RV32I-FPELIM-NEXT: sw a1, 8(a0)
; RV32I-FPELIM-NEXT: li a1, 4
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
; RV32I-FPELIM-NEXT: sw a2, 4(a0)
; RV32I-FPELIM-NEXT: sw a3, 8(a0)
; RV32I-FPELIM-NEXT: sw a4, 12(a0)
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_large_struct_ret:
Expand All @@ -954,13 +954,13 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: li a1, 1
; RV32I-WITHFP-NEXT: li a2, 2
; RV32I-WITHFP-NEXT: li a3, 3
; RV32I-WITHFP-NEXT: li a4, 4
; RV32I-WITHFP-NEXT: sw a1, 0(a0)
; RV32I-WITHFP-NEXT: li a1, 2
; RV32I-WITHFP-NEXT: sw a1, 4(a0)
; RV32I-WITHFP-NEXT: li a1, 3
; RV32I-WITHFP-NEXT: sw a1, 8(a0)
; RV32I-WITHFP-NEXT: li a1, 4
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: sw a2, 4(a0)
; RV32I-WITHFP-NEXT: sw a3, 8(a0)
; RV32I-WITHFP-NEXT: sw a4, 12(a0)
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -203,8 +203,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a0, 262816
; RV32-ILP32D-NEXT: sw a0, 4(sp)
; RV32-ILP32D-NEXT: lui a1, 262816
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI9_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
Expand All @@ -225,6 +224,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-NEXT: li a2, 3
; RV32-ILP32D-NEXT: li a4, 5
; RV32-ILP32D-NEXT: li a6, 7
; RV32-ILP32D-NEXT: sw a1, 4(sp)
; RV32-ILP32D-NEXT: sw zero, 0(sp)
; RV32-ILP32D-NEXT: li a1, 0
; RV32-ILP32D-NEXT: li a3, 0
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -82,15 +82,15 @@ define i32 @caller_many_scalars() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a0, 8
; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: li a4, 8
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: li a2, 3
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a5, 5
; RV64I-NEXT: li a6, 6
; RV64I-NEXT: li a7, 7
; RV64I-NEXT: sd a4, 8(sp)
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call callee_many_scalars@plt
Expand Down Expand Up @@ -189,9 +189,9 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, sp, 16
; RV64I-NEXT: li a1, 9
; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: li a0, 9
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 24(sp)
Expand Down Expand Up @@ -356,24 +356,24 @@ define void @caller_aligned_stack() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a0, 12
; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: li a0, 11
; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: li a0, 10
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: li a0, 9
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: li a6, 8
; RV64I-NEXT: li a6, 12
; RV64I-NEXT: li t0, 11
; RV64I-NEXT: li t1, 10
; RV64I-NEXT: li t2, 9
; RV64I-NEXT: li t3, 8
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: li a2, 3
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 5
; RV64I-NEXT: li a5, 6
; RV64I-NEXT: li a7, 7
; RV64I-NEXT: sd a6, 0(sp)
; RV64I-NEXT: sd a6, 48(sp)
; RV64I-NEXT: sd t0, 40(sp)
; RV64I-NEXT: sd t1, 32(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd t2, 16(sp)
; RV64I-NEXT: sd t3, 0(sp)
; RV64I-NEXT: li a6, 0
; RV64I-NEXT: call callee_aligned_stack@plt
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -449,12 +449,12 @@ define i256 @callee_large_scalar_ret() nounwind {
; RV64I-LABEL: callee_large_scalar_ret:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: lui a2, 1018435
; RV64I-NEXT: addiw a2, a2, 747
; RV64I-NEXT: sd a1, 24(a0)
; RV64I-NEXT: sd a1, 16(a0)
; RV64I-NEXT: sd a1, 8(a0)
; RV64I-NEXT: lui a1, 1018435
; RV64I-NEXT: addiw a1, a1, 747
; RV64I-NEXT: sd a1, 0(a0)
; RV64I-NEXT: sd a2, 0(a0)
; RV64I-NEXT: ret
ret i256 -123456789
}
Expand All @@ -478,18 +478,18 @@ define void @caller_large_scalar_ret() nounwind {
define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result) nounwind {
; RV64I-LABEL: callee_large_struct_ret:
; RV64I: # %bb.0:
; RV64I-NEXT: sw zero, 4(a0)
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: li a2, 2
; RV64I-NEXT: sw zero, 4(a0)
; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: li a1, 3
; RV64I-NEXT: sw zero, 12(a0)
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: sw a1, 8(a0)
; RV64I-NEXT: sw a2, 8(a0)
; RV64I-NEXT: li a2, 4
; RV64I-NEXT: sw zero, 20(a0)
; RV64I-NEXT: li a1, 3
; RV64I-NEXT: sw a1, 16(a0)
; RV64I-NEXT: sw zero, 28(a0)
; RV64I-NEXT: li a1, 4
; RV64I-NEXT: sw a1, 24(a0)
; RV64I-NEXT: sw a2, 24(a0)
; RV64I-NEXT: ret
store i64 1, ptr %agg.result, align 4
%b = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 1
Expand Down
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