[MIPS] Fix missing ANDI optimization (#97689)

1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to (andi
(truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to (truncate
(dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fixes #42826

llvm/lib/Target/Mips/Mips64InstrInfo.td

@@ -830,6 +830,12 @@ def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
               ISA_MIPS3, GPR_64;
+def : MipsPat<(and (srl (i32 (trunc GPR64:$src)), immZExt5:$imm5), immZExt16:$value),
+              (ANDi (EXTRACT_SUBREG (DSRL GPR64:$src, immZExt5:$imm5), sub_32), immZExt16:$value)>,
+              ISA_MIPS3, GPR_64;
+def : MipsPat<(MipsExt (i32 (trunc GPR64:$src)), immZExt5:$pos, immZExt5:$size),
+              (EXTRACT_SUBREG (DEXT GPR64:$src, immZExt5:$pos, immZExt5:$size), sub_32)>,
+              ISA_MIPS3, GPR_64;
 
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)),

llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll

@@ -6,17 +6,15 @@
 define i64 @foo(i64 noundef %a) {
 ; MIPS4-LABEL: foo:
 ; MIPS4:       # %bb.0: # %entry
-; MIPS4-NEXT:   sll    $1, $4, 0
-; MIPS4-NEXT:   srl    $1, $1, 2
+; MIPS4-NEXT:   dsrl   $1, $4, 2
 ; MIPS4-NEXT:   andi   $1, $1, 7
 ; MIPS4-NEXT:   daddiu $2, $zero, 1
 ; MIPS4-NEXT:   jr     $ra
 ; MIPS4-NEXT:   dsllv  $2, $2, $1
 ;
 ; MIPS64R2-LABEL: foo:
 ; MIPS64R2:       # %bb.0: # %entry
-; MIPS64R2-NEXT:   sll	  $1, $4, 0
-; MIPS64R2-NEXT:   ext	  $1, $1, 2, 3
+; MIPS64R2-NEXT:   dext	  $1, $4, 2, 3
 ; MIPS64R2-NEXT:   daddiu $2, $zero, 1
 ; MIPS64R2-NEXT:   jr     $ra
 ; MIPS64R2-NEXT:   dsllv  $2, $2, $1