[RISCV] Add TuneNoSinkSplatOperands to sifive-p670 (#79492)

llvm · Jan 26, 2024 · f13aac6 · f13aac6
1 parent 63fe80f
commit f13aac6
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -280,7 +280,8 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
                                       [TuneNoDefaultUnroll,
                                        TuneConditionalCompressedMoveFusion,
                                        TuneLUIADDIFusion,
-                                       TuneAUIPCADDIFusion]>;
+                                       TuneAUIPCADDIFusion,
+                                       TuneNoSinkSplatOperands]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,