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Legalize drops conditions and selects #1024
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Hrm, I get: $LBBl5_l14_g721_encoder_then_2E_i_3: # then.i When I just use LLC. Do I need some special flags? -Chris |
note, it's also possible that legalize is folding things in a different order for you than for me. Can you try -Chris |
here is some relivent debug output, still tracking down the line that does this. Replacing 0x120f14010: ch = TokenFactor 0x120f13fb0, 0x120f122d0 Replacing 0x120f13bd0: i16 = select 0x120f13b70, 0x120f13d30, 0x120f13da0 Replacing 0x120f14430: i16 = shl 0x120f14360, 0x120f143c0 Replacing 0x120f13e80: i1 = setcc 0x120f13da0, 0x120f13da0, 0x120f13e10 Replacing 0x120f14260: ch = brcondtwoway 0x120f13fb0, 0x120f14430, 0x120f14070, |
DAGCombiner.cpp:2172 is causing this. |
wait, how did that constant get positive? DAG shows it is selected to |
Fixed. Thanks Chris. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20051031/029214.html |
'add r2, #-1024' should just use 'sub r2, llvm#1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 llvm-svn: 154123
This patch does 3 things: 1. Add support for optimizing the address mode of HVX load/store instructions 2. Reduce the value of Add instruction immediates by replacing with the difference from other Addi instructions that share common base: For Example, If we have the below sequence of instructions: r1 = add(r2,llvm#1024) ... r3 = add(r2,llvm#1152) ... r4 = add(r2,llvm#1280) Where the register r2 has the same reaching definition, They get modified to the below sequence: r1 = add(r2,llvm#1024) ... r3 = add(r1,llvm#128) ... r4 = add(r1,llvm#256) 3. Fixes a bug pass where the addi instructions were modified based on a predicated register definition, leading to incorrect output. Eg: INST-1: if (p0) r2 = add(r13,llvm#128) INST-2: r1 = add(r2,llvm#1024) INST-3: r3 = add(r2,llvm#1152) INST-4: r5 = add(r2,llvm#1280) In the above case, since r2's definition is predicated, we do not want to modify the uses of r2 in INST-3/INST-4 with add(r1,llvm#128/256) 4.Fixes a corner case It looks like we never check whether the offset register is actually live (not clobbered) at optimization site. Add the check whether it is live at MBB entrance. The rest should have already been verified. 5. Fixes a bad codegen For whatever reason we do transformation without checking if the value in register actually reaches the user. This is second identical fix for this pass. Co-authored-by: Anirudh Sundar <quic_sanirudh@quicinc.com> Co-authored-by: Sergei Larin <slarin@quicinc.com>
Extended Description
Legalize makes the last block mostly disappear, and that is bad.
; ModuleID = 'bugpoint.test.bc'
target endian = little
target pointersize = 64
implementation ; Functions:
bool %l5_l14_g721_encoder_then_2E_i(int %tmp.46.reload, short* %tmp.5542.out) {
newFuncRoot:
br label %then.i
cond_true.exitStub: ; preds = %then.i
store short %tmp.5542, short* %tmp.5542.out
ret bool true
cond_false.exitStub: ; preds = %then.i
store short %tmp.5542, short* %tmp.5542.out
ret bool false
then.i: ; preds = %newFuncRoot
%tmp.11.i = setne int %tmp.46.reload, 0 ; [#uses=1]
%tmp.5542 = select bool %tmp.11.i, short -32768, short 0
; [#uses=3]
%tmp.5744 = setlt short %tmp.5542, 0 ; [#uses=1]
br bool %tmp.5744, label %cond_true.exitStub, label %cond_false.exitStub
}
Gets codegened into:
newFuncRoot:
%$31 = BR mbb<then.i,0x120f11190>
cond_true.exitStub:
STW %$0, 0, %$17
%$0 = LDA 1, %$31
%$31 = RET %$26, 1
cond_false.exitStub:
STW %$0, 0, %$17
%$0 = LDA 0, %$31
%$31 = RET %$26, 1
then.i:
%$0 = LDA 0, %$31
%$31 = BR mbb<cond_false.exitStub,0x120f110d0>
then.i is clearly in bad shape.
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