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[clang] Miscompilation at -O2/3 #122496
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EugeneZelenko
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Clang issues not falling into any other category
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Jan 10, 2025
Bisecting now |
Reproducer: https://godbolt.org/z/6bzT9rs3K
llubi output: Before:
After:
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fhahn
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Jan 12, 2025
Use the existing VPlan-based analysis to identify recipes that only have their first lane demanded and transform them to uniform recpliate recipes. This simplifies the generated code in some places and prepares for fixing #122496.
github-actions bot
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…orm recipes. Use the existing VPlan-based analysis to identify recipes that only have their first lane demanded and transform them to uniform recpliate recipes. This simplifies the generated code in some places and prepares for fixing llvm/llvm-project#122496.
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… used outside. In some cases, there might be a chain of uniform instructions producing the exit value. To generate correct code in all cases, consider the IV increment not uniform, if there are users outside the loop. Instead, let VPlan narrow the IV, if possible using the logic from 3ff1d01. Test case from #122602 verified with Alive2: https://alive2.llvm.org/ce/z/bA4EGj Fixes llvm/llvm-project#122496. Fixes llvm/llvm-project#122602.
shenhanc78
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Jan 13, 2025
Use the existing VPlan-based analysis to identify recipes that only have their first lane demanded and transform them to uniform recpliate recipes. This simplifies the generated code in some places and prepares for fixing llvm#122496.
shenhanc78
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Jan 13, 2025
Add test cases for llvm#122496 and llvm#122602.
shenhanc78
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Jan 13, 2025
In some cases, there might be a chain of uniform instructions producing the exit value. To generate correct code in all cases, consider the IV increment not uniform, if there are users outside the loop. Instead, let VPlan narrow the IV, if possible using the logic from 3ff1d01. Test case from llvm#122602 verified with Alive2: https://alive2.llvm.org/ce/z/bA4EGj Fixes llvm#122496. Fixes llvm#122602.
Mel-Chen
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Use the existing VPlan-based analysis to identify recipes that only have their first lane demanded and transform them to uniform recpliate recipes. This simplifies the generated code in some places and prepares for fixing llvm#122496.
Mel-Chen
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Jan 13, 2025
Add test cases for llvm#122496 and llvm#122602.
Mel-Chen
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Jan 13, 2025
In some cases, there might be a chain of uniform instructions producing the exit value. To generate correct code in all cases, consider the IV increment not uniform, if there are users outside the loop. Instead, let VPlan narrow the IV, if possible using the logic from 3ff1d01. Test case from llvm#122602 verified with Alive2: https://alive2.llvm.org/ce/z/bA4EGj Fixes llvm#122496. Fixes llvm#122602.
DKLoehr
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Jan 17, 2025
Use the existing VPlan-based analysis to identify recipes that only have their first lane demanded and transform them to uniform recpliate recipes. This simplifies the generated code in some places and prepares for fixing llvm#122496.
DKLoehr
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Jan 17, 2025
Add test cases for llvm#122496 and llvm#122602.
DKLoehr
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Jan 17, 2025
In some cases, there might be a chain of uniform instructions producing the exit value. To generate correct code in all cases, consider the IV increment not uniform, if there are users outside the loop. Instead, let VPlan narrow the IV, if possible using the logic from 3ff1d01. Test case from llvm#122602 verified with Alive2: https://alive2.llvm.org/ce/z/bA4EGj Fixes llvm#122496. Fixes llvm#122602.
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This code prints 0 at
-O0/1
and triggers SIGKILL at-O2/3
:Compiler Explorer: https://godbolt.org/z/3x8Yc3fnW
It seems to be a recent regression.
The text was updated successfully, but these errors were encountered: