Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[LoongArch] Assertion `isReg() && "This is not a register operand!"' #79718

Closed
DianQK opened this issue Jan 28, 2024 · 4 comments · Fixed by #79820
Closed

[LoongArch] Assertion `isReg() && "This is not a register operand!"' #79718

DianQK opened this issue Jan 28, 2024 · 4 comments · Fixed by #79820

Comments

@DianQK
Copy link
Member

DianQK commented Jan 28, 2024

I tried this code with llc --mtriple=loongarch64

define void @foo(ptr nocapture writeonly %0, i1 %1, i1 %2, i1 %3, i1 %4) {
start:
  br label %bb1

bb1:                                              ; preds = %bb6, %start
  %5 = phi i64 [ 0, %start ], [ %20, %bb6 ]
  %6 = phi i64 [ 0, %start ], [ %21, %bb6 ]
  %7 = phi i64 [ undef, %start ], [ %23, %bb6 ]
  %8 = icmp eq i64 %5, 1
  br label %bb2

bb2:                                              ; preds = %bb6, %bb1
  %9 = phi i64 [ %5, %bb1 ], [ %20, %bb6 ]
  %10 = phi i64 [ %6, %bb1 ], [ %21, %bb6 ]
  %11 = phi i64 [ %6, %bb1 ], [ %22, %bb6 ]
  %12 = phi i64 [ %7, %bb1 ], [ %23, %bb6 ]
  br i1 %1, label %loopexit, label %preheader

preheader:                                        ; preds = %bb2, %bb4
  %13 = phi i64 [ %15, %bb4 ], [ %11, %bb2 ]
  %14 = load volatile { i64, i64 }, ptr null, align 4294967296
  br i1 %2, label %bb3, label %bb5

bb3:                                              ; preds = %preheader
  %15 = add i64 %13, 1
  br i1 %3, label %bb4, label %bb5

bb4:                                              ; preds = %bb3
  br i1 %4, label %loopexit, label %preheader

loopexit:                                         ; preds = %bb4, %bb2
  %16 = phi i64 [ %10, %bb2 ], [ %15, %bb4 ]
  %17 = phi i64 [ %11, %bb2 ], [ %15, %bb4 ]
  store i8 0, ptr %0, align 1
  br label %bb6

bb5:                                              ; preds = %bb3, %preheader
  %18 = phi i64 [ 1, %bb3 ], [ 0, %preheader ]
  %19 = phi i64 [ %15, %bb3 ], [ %12, %preheader ]
  store i64 0, ptr %0, align 8
  br label %bb6

bb6:                                              ; preds = %bb5, %loopexit
  %20 = phi i64 [ %19, %bb5 ], [ %9, %loopexit ]
  %21 = phi i64 [ %18, %bb5 ], [ %16, %loopexit ]
  %22 = phi i64 [ %18, %bb5 ], [ %17, %loopexit ]
  %23 = phi i64 [ %19, %bb5 ], [ %12, %loopexit ]
  br i1 %8, label %bb2, label %bb1
}

I got a segmentation fault.
If assertion is turned on, I can get isReg() && "This is not a register operand!"' failed.

GodBolt: https://llvm.godbolt.org/z/zT5rKrW6x
From: rust-lang/rust#120268

@DianQK
Copy link
Member Author

DianQK commented Jan 28, 2024

I'll try to fix that. But if anyone intends to fix that, please ignore me and submit a PR. :)
(For unfamiliar places, I can only fix them by intuition.)

DianQK added a commit that referenced this issue Feb 9, 2024
… but erased (#79820)

Fixes #79718. Fixes #71178.

The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.
@DianQK
Copy link
Member Author

DianQK commented Feb 9, 2024

Reopen for backport. Since I modified the MIR output, this may make future backports difficult?

@DianQK DianQK reopened this Feb 9, 2024
@nikic nikic added this to the LLVM 18.X Release milestone Feb 9, 2024
@DianQK
Copy link
Member Author

DianQK commented Feb 9, 2024

/cherry-pick 95b14da

llvmbot pushed a commit to llvmbot/llvm-project that referenced this issue Feb 9, 2024
… but erased (llvm#79820)

Fixes llvm#79718. Fixes llvm#71178.

The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.

(cherry picked from commit 95b14da)
@llvmbot llvmbot closed this as completed Feb 9, 2024
@llvmbot
Copy link
Collaborator

llvmbot commented Feb 9, 2024

/pull-request #81241

llvmbot pushed a commit to llvmbot/llvm-project that referenced this issue Feb 9, 2024
… but erased (llvm#79820)

Fixes llvm#79718. Fixes llvm#71178.

The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.

(cherry picked from commit 95b14da)
tstellar pushed a commit to tstellar/llvm-project that referenced this issue Feb 14, 2024
… but erased (llvm#79820)

Fixes llvm#79718. Fixes llvm#71178.

The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.

(cherry picked from commit 95b14da)
tstellar pushed a commit to tstellar/llvm-project that referenced this issue Feb 14, 2024
… but erased (llvm#79820)

Fixes llvm#79718. Fixes llvm#71178.

The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.

(cherry picked from commit 95b14da)
tstellar pushed a commit to tstellar/llvm-project that referenced this issue Feb 14, 2024
… but erased (llvm#79820)

Fixes llvm#79718. Fixes llvm#71178.

The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.

(cherry picked from commit 95b14da)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
Development

Successfully merging a pull request may close this issue.

4 participants