[X86ISelLowering] MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.

[DianQK]

I tried this code:

target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define <2 x i128> @foo(i128 %arg) #0 {
bb:
  %i = xor i128 %arg, 1
  %i1 = insertelement <2 x i128> zeroinitializer, i128 %i, i64 0
  %i2 = shufflevector <2 x i128> %i1, <2 x i128> zeroinitializer, <2 x i32> zeroinitializer
  %i3 = and <2 x i128> <i128 1, i128 1>, %i2
  ret <2 x i128> %i3
}

attributes #0 = { "target-cpu"="sandybridge" }

I got the following error log:

llc: /home/dianqk/llvm/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:289: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /home/dianqk/llvm/llvm-project/build/bin/llc /home/dianqk/llvm/rust-122252/foo.ll -filetype=null
1.      Running pass 'Function Pass Manager' on module '/home/dianqk/llvm/rust-122252/foo.ll'.
2.      Running pass 'X86 DAG->DAG Instruction Selection' on function '@foo'
...
 #9 0x00007f9594e587ce llvm::LinearPolySize<llvm::TypeSize>::getFixedValue() const /home/dianqk/llvm/llvm-project/llvm/include/llvm/Support/TypeSize.h:314:5
#10 0x00007f9594e587ce llvm::TypeSize::getFixedSize() const /home/dianqk/llvm/llvm-project/llvm/include/llvm/Support/TypeSize.h:456:52
#11 0x00007f9594e587ce llvm::MVT::getScalarSizeInBits() const /home/dianqk/llvm/llvm-project/llvm/include/llvm/Support/MachineValueType.h:1139:46
#12 0x00007f9594e587ce combineAndnp(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) /home/dianqk/llvm/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:52218:31
#13 0x00007f9594e31658 llvm::X86TargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const /home/dianqk/llvm/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:0:36
...

Bisected to 15dd5ed.

Godbolt: https://llvm.godbolt.org/z/o9fEqj8x5
From: rust-lang/rust#122252

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Quentin Dian (DianQK)

I tried this code:

target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define void @<!-- -->foo(i128 %arg) #<!-- -->0 {
bb:
  %i = xor i128 %arg, 1
  %i1 = insertelement &lt;2 x i128&gt; zeroinitializer, i128 %i, i64 0
  %i2 = shufflevector &lt;2 x i128&gt; %i1, &lt;2 x i128&gt; zeroinitializer, &lt;2 x i32&gt; zeroinitializer
  %i3 = and &lt;2 x i128&gt; &lt;i128 1, i128 1&gt;, %i2
  %i4 = trunc &lt;2 x i128&gt; %i3 to &lt;2 x i32&gt;
  store &lt;2 x i32&gt; %i4, ptr null, align 8
  ret void
}

attributes #<!-- -->0 = { "target-cpu"="sandybridge" }

I got following error log:

llc: /home/dianqk/llvm/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:289: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /home/dianqk/llvm/llvm-project/build/bin/llc /home/dianqk/llvm/rust-122252/foo.ll -filetype=null
1.      Running pass 'Function Pass Manager' on module '/home/dianqk/llvm/rust-122252/foo.ll'.
2.      Running pass 'X86 DAG-&gt;DAG Instruction Selection' on function '@<!-- -->foo'
...
 #<!-- -->9 0x00007f9594e587ce llvm::LinearPolySize&lt;llvm::TypeSize&gt;::getFixedValue() const /home/dianqk/llvm/llvm-project/llvm/include/llvm/Support/TypeSize.h:314:5
#<!-- -->10 0x00007f9594e587ce llvm::TypeSize::getFixedSize() const /home/dianqk/llvm/llvm-project/llvm/include/llvm/Support/TypeSize.h:456:52
#<!-- -->11 0x00007f9594e587ce llvm::MVT::getScalarSizeInBits() const /home/dianqk/llvm/llvm-project/llvm/include/llvm/Support/MachineValueType.h:1139:46
#<!-- -->12 0x00007f9594e587ce combineAndnp(llvm::SDNode*, llvm::SelectionDAG&amp;, llvm::TargetLowering::DAGCombinerInfo&amp;, llvm::X86Subtarget const&amp;) /home/dianqk/llvm/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:52218:31
#<!-- -->13 0x00007f9594e31658 llvm::X86TargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&amp;) const /home/dianqk/llvm/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:0:36
...

Godbolt: https://llvm.godbolt.org/z/4WvMGc59b
From: rust-lang/rust#122252

[DianQK]

Perhaps we need this patch?

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e1e6c22eb8cc..2b3a2b684366 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48142,6 +48142,8 @@ static SDValue combineAndShuffleNot(SDNode *N, SelectionDAG &DAG,
   assert(N->getOpcode() == ISD::AND && "Unexpected opcode combine into ANDNP");
 
   EVT VT = N->getValueType(0);
+  if (!VT.isSimple())
+    return SDValue();
   // Do not split 256 and 512 bit vectors with SSE2 as they overwrite original
   // value and require extra moves.
   if (!((VT.is128BitVector() && Subtarget.hasSSE2()) ||

cc @e-kud @phoebewang @RKSimon

[DianQK]

Thanks for the fix!
/cherry-pick 862c7e0

[llvmbot]

/pull-request #84698