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Update load intrinsic attributes #101562

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merged 6 commits into from
Aug 15, 2024
Merged

Update load intrinsic attributes #101562

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ef47e3d
Add IntrWillReturn to intrinsics
kalxr Aug 1, 2024
725139a
Add DCE test for modified intrinsics
kalxr Aug 6, 2024
1155f36
Add missing tests
kalxr Aug 6, 2024
663a518
Use DefaultAttrsIntrinsic instead for most intrinsics
kalxr Aug 7, 2024
2546ab1
Split tests into per-target files and consolidate existing nvvm test
kalxr Aug 7, 2024
64b6cf4
[LoongArch] Create and use DefaultAttrsVecInt instead of IntrWillReturn
kalxr Aug 8, 2024
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6 changes: 3 additions & 3 deletions llvm/include/llvm/IR/IntrinsicsBPF.td
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Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,11 @@
// Specialized loads from packet
let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf."
def int_bpf_load_byte : ClangBuiltin<"__builtin_bpf_load_byte">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem]>;
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem]>;
def int_bpf_load_half : ClangBuiltin<"__builtin_bpf_load_half">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem]>;
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem]>;
def int_bpf_load_word : ClangBuiltin<"__builtin_bpf_load_word">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem]>;
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem]>;
def int_bpf_pseudo : ClangBuiltin<"__builtin_bpf_pseudo">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty]>;
def int_bpf_preserve_field_info : ClangBuiltin<"__builtin_bpf_preserve_field_info">,
Expand Down
24 changes: 12 additions & 12 deletions llvm/include/llvm/IR/IntrinsicsLoongArch.td
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Expand Up @@ -621,22 +621,22 @@ foreach inst = ["vfcmp_caf_d", "vfcmp_cun_d", "vfcmp_ceq_d", "vfcmp_cueq_d",
// LSX load/store
def int_loongarch_lsx_vld
: VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
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Use default attrs here as well? From a quick search, these are normal (non-synchronizing) vector loads.

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Originally avoided since these inherit from VecInt, but created class DefaultAttrsVecInt which inherits from DefaultAttrsIntrinsic instead of Intrinsic which should accomplish this.

def int_loongarch_lsx_vldx
: VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i64_ty],
[IntrReadMem, IntrArgMemOnly]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly]>;
def int_loongarch_lsx_vldrepl_b
: VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lsx_vldrepl_h
: VecInt<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lsx_vldrepl_w
: VecInt<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lsx_vldrepl_d
: VecInt<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;

def int_loongarch_lsx_vst
: VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty],
Expand Down Expand Up @@ -1147,22 +1147,22 @@ def int_loongarch_lasx_xvpickve_d_f
// LASX load/store
def int_loongarch_lasx_xvld
: VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lasx_xvldx
: VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i64_ty],
[IntrReadMem, IntrArgMemOnly]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly]>;
def int_loongarch_lasx_xvldrepl_b
: VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lasx_xvldrepl_h
: VecInt<[llvm_v16i16_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lasx_xvldrepl_w
: VecInt<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
def int_loongarch_lasx_xvldrepl_d
: VecInt<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;

def int_loongarch_lasx_xvst
: VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty],
Expand Down
26 changes: 13 additions & 13 deletions llvm/include/llvm/IR/IntrinsicsMips.td
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Expand Up @@ -236,7 +236,7 @@ def int_mips_extpdp: ClangBuiltin<"__builtin_mips_extpdp">,
def int_mips_wrdsp: ClangBuiltin<"__builtin_mips_wrdsp">,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
def int_mips_rddsp: ClangBuiltin<"__builtin_mips_rddsp">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem, ImmArg<ArgIndex<0>>]>;
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem, ImmArg<ArgIndex<0>>]>;

def int_mips_insv: ClangBuiltin<"__builtin_mips_insv">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
Expand All @@ -252,22 +252,22 @@ def int_mips_repl_ph: ClangBuiltin<"__builtin_mips_repl_ph">,
Intrinsic<[mips_v2q15_ty], [llvm_i32_ty], [IntrNoMem]>;

def int_mips_pick_qb: ClangBuiltin<"__builtin_mips_pick_qb">,
Intrinsic<[llvm_v4i8_ty], [llvm_v4i8_ty, llvm_v4i8_ty], [IntrReadMem]>;
DefaultAttrsIntrinsic<[llvm_v4i8_ty], [llvm_v4i8_ty, llvm_v4i8_ty], [IntrReadMem]>;
def int_mips_pick_ph: ClangBuiltin<"__builtin_mips_pick_ph">,
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Intrinsic<[mips_v2q15_ty], [mips_v2q15_ty, mips_v2q15_ty], [IntrReadMem]>;
DefaultAttrsIntrinsic<[mips_v2q15_ty], [mips_v2q15_ty, mips_v2q15_ty], [IntrReadMem]>;

def int_mips_mthlip: ClangBuiltin<"__builtin_mips_mthlip">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty], []>;

def int_mips_bposge32: ClangBuiltin<"__builtin_mips_bposge32">,
Intrinsic<[llvm_i32_ty], [], [IntrReadMem]>;
DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrReadMem]>;

def int_mips_lbux: ClangBuiltin<"__builtin_mips_lbux">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
def int_mips_lhx: ClangBuiltin<"__builtin_mips_lhx">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
def int_mips_lwx: ClangBuiltin<"__builtin_mips_lwx">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;

//===----------------------------------------------------------------------===//
// MIPS DSP Rev 2
Expand Down Expand Up @@ -1259,23 +1259,23 @@ def int_mips_insve_d : ClangBuiltin<"__builtin_msa_insve_d">,
[IntrNoMem, ImmArg<ArgIndex<1>>]>;

def int_mips_ld_b : ClangBuiltin<"__builtin_msa_ld_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly]>;
def int_mips_ld_h : ClangBuiltin<"__builtin_msa_ld_h">,
Intrinsic<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly]>;
def int_mips_ld_w : ClangBuiltin<"__builtin_msa_ld_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly]>;
def int_mips_ld_d : ClangBuiltin<"__builtin_msa_ld_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly]>;

def int_mips_ldr_d : ClangBuiltin<"__builtin_msa_ldr_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly]>;
def int_mips_ldr_w : ClangBuiltin<"__builtin_msa_ldr_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly]>;

def int_mips_ldi_b : ClangBuiltin<"__builtin_msa_ldi_b">,
Expand Down
2 changes: 1 addition & 1 deletion llvm/include/llvm/IR/IntrinsicsNVVM.td
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Expand Up @@ -4699,7 +4699,7 @@ def int_nvvm_redux_sync_or : ClangBuiltin<"__nvvm_redux_sync_or">,
class NVVM_WMMA_LD<WMMA_REGS Frag, string Layout, int WithStride>
: Intrinsic<Frag.regs,
!if(WithStride, [llvm_anyptr_ty, llvm_i32_ty], [llvm_anyptr_ty]),
[IntrReadMem, IntrArgMemOnly, IntrNoCallback, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>],
[IntrWillReturn, IntrReadMem, IntrArgMemOnly, IntrNoCallback, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>],
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@jholewinski I think this is fine, but then wonder why it is only added to this one intrinsic.
Might be worth opening an issue to not forget giving all intrinsics in this file a "should this be willreturn pass?".
Thoughts?

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For some extra context, this batch of changes was motivated by #99999 which slightly changes some behavior related to intrinsics that are treated as loads in the SDAG. Of the NVVM intrinsics affected by that, this was the only one that seemed to be missing WillReturn. Earlier, #98968 updated some other similar cases. There are likely more intrinsics that should have WillReturn or inherit the default attributes that are not addressed in this patch due to being unaffected by the SDAG change.

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Ah thanks, sorry missed that. Makes sense :)

WMMA_NAME_LDST<"load", Frag, Layout, WithStride>.intr>;

// WMMA.STORE.D
Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/IR/IntrinsicsSystemZ.td
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Expand Up @@ -230,11 +230,11 @@ let TargetPrefix = "s390" in {
[IntrNoMem, ImmArg<ArgIndex<1>>]>;

def int_s390_vlbb : ClangBuiltin<"__builtin_s390_vlbb">,
Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;

def int_s390_vll : ClangBuiltin<"__builtin_s390_vll">,
Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty],
DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty],
[IntrReadMem, IntrArgMemOnly]>;

def int_s390_vpdi : ClangBuiltin<"__builtin_s390_vpdi">,
Expand Down Expand Up @@ -399,7 +399,7 @@ let TargetPrefix = "s390" in {

// Instructions from the Vector Packed Decimal Facility
def int_s390_vlrl : ClangBuiltin<"__builtin_s390_vlrlr">,
Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty],
DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty],
[IntrReadMem, IntrArgMemOnly]>;

def int_s390_vstrl : ClangBuiltin<"__builtin_s390_vstrlr">,
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/IR/IntrinsicsVE.td
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Expand Up @@ -3,10 +3,10 @@
// VEL Intrinsic instructions.
let TargetPrefix = "ve" in {
def int_ve_vl_pack_f32p : ClangBuiltin<"__builtin_ve_vl_pack_f32p">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty],
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty],
[IntrReadMem]>;
def int_ve_vl_pack_f32a : ClangBuiltin<"__builtin_ve_vl_pack_f32a">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty],
[IntrReadMem]>;

def int_ve_vl_extract_vm512u :
Expand Down
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