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[DAG] Add select_cc -> abd folds #102137

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Aug 21, 2024
Merged

[DAG] Add select_cc -> abd folds #102137

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0a34073
[DAG] Add select_cc -> abd folds
RKSimon Aug 6, 2024
844cd1a
[AArch64] Regenerate abds-neg.ll
RKSimon Aug 21, 2024
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2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27919,6 +27919,8 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
return S;
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG))
return S;
if (SDValue ABD = foldSelectToABD(N0, N1, N2, N3, CC, DL))
return ABD;

return SDValue();
}
Expand Down
17 changes: 8 additions & 9 deletions llvm/test/CodeGen/AArch64/abds-neg.ll
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Expand Up @@ -377,7 +377,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x8, x9, lt
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: ret
%cmp = icmp slt i64 %a, %b
%ab = sub i64 %a, %b
Expand All @@ -389,14 +389,13 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: sbc x8, x1, x3
; CHECK-NEXT: subs x9, x2, x0
; CHECK-NEXT: sbc x10, x3, x1
; CHECK-NEXT: subs x11, x0, x2
; CHECK-NEXT: sbcs xzr, x1, x3
; CHECK-NEXT: csel x0, x9, x11, lt
; CHECK-NEXT: csel x1, x10, x8, lt
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
; CHECK-NEXT: sbc x11, x3, x1
; CHECK-NEXT: sbcs xzr, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
%cmp = icmp slt i128 %a, %b
%ab = sub i128 %a, %b
Expand Down
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/AArch64/abds.ll
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Expand Up @@ -298,10 +298,9 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, sxtb
; CHECK-NEXT: csel w0, w9, w10, gt
; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sgt i8 %a, %b
%ab = sub i8 %a, %b
Expand All @@ -314,10 +313,9 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, sxth
; CHECK-NEXT: csel w0, w9, w10, ge
; CHECK-NEXT: sub w8, w8, w1, sxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp sge i16 %a, %b
%ab = sub i16 %a, %b
Expand All @@ -331,7 +329,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w8, w9, lt
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%cmp = icmp slt i32 %a, %b
%ab = sub i32 %a, %b
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/AArch64/abdu-neg.ll
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Expand Up @@ -379,7 +379,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x8, x9, lo
; CHECK-NEXT: csel x0, x9, x8, hi
; CHECK-NEXT: ret
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
Expand All @@ -391,14 +391,14 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: sbc x8, x1, x3
; CHECK-NEXT: subs x9, x2, x0
; CHECK-NEXT: sbc x10, x3, x1
; CHECK-NEXT: subs x11, x0, x2
; CHECK-NEXT: sbcs xzr, x1, x3
; CHECK-NEXT: csel x0, x9, x11, lo
; CHECK-NEXT: csel x1, x10, x8, lo
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbcs x9, x1, x3
; CHECK-NEXT: cset w10, lo
; CHECK-NEXT: sbfx x10, x10, #0, #1
; CHECK-NEXT: eor x8, x8, x10
; CHECK-NEXT: eor x9, x9, x10
; CHECK-NEXT: subs x0, x8, x10
; CHECK-NEXT: sbc x1, x9, x10
; CHECK-NEXT: ret
%cmp = icmp ult i128 %a, %b
%ab = sub i128 %a, %b
Expand Down
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/AArch64/abdu.ll
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Expand Up @@ -301,10 +301,9 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, uxtb
; CHECK-NEXT: csel w0, w9, w10, hi
; CHECK-NEXT: sub w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ugt i8 %a, %b
%ab = sub i8 %a, %b
Expand All @@ -317,10 +316,9 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, uxth
; CHECK-NEXT: csel w0, w9, w10, hs
; CHECK-NEXT: sub w8, w8, w1, uxth
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret
%cmp = icmp uge i16 %a, %b
%ab = sub i16 %a, %b
Expand All @@ -334,7 +332,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
%cmp = icmp ult i32 %a, %b
%ab = sub i32 %a, %b
Expand Down
21 changes: 8 additions & 13 deletions llvm/test/CodeGen/AMDGPU/sad.ll
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Expand Up @@ -258,10 +258,9 @@ define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out
; GCN-NEXT: s_add_u32 s16, s16, s13
; GCN-NEXT: s_addc_u32 s17, s17, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_sub_i32 s3, s0, s1
; GCN-NEXT: s_sub_i32 s6, s1, s0
; GCN-NEXT: s_cmp_gt_u32 s0, s1
; GCN-NEXT: s_cselect_b32 s0, s3, s6
; GCN-NEXT: s_min_u32 s3, s0, s1
; GCN-NEXT: s_max_u32 s0, s0, s1
; GCN-NEXT: s_sub_i32 s0, s0, s3
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: s_add_i32 s0, s0, s2
Expand Down Expand Up @@ -477,18 +476,14 @@ define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext %
; GCN-NEXT: s_load_dword s2, s[6:7], 0x2
; GCN-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s4, s2, 8
; GCN-NEXT: s_and_b32 s3, s2, 0xff
; GCN-NEXT: s_bfe_u32 s5, s2, 0x80008
; GCN-NEXT: s_lshr_b32 s6, s2, 16
; GCN-NEXT: s_sub_i32 s7, s2, s4
; GCN-NEXT: s_sub_i32 s2, s4, s2
; GCN-NEXT: s_cmp_gt_u32 s3, s5
; GCN-NEXT: s_cselect_b32 s2, s7, s2
; GCN-NEXT: s_add_i32 s2, s2, s6
; GCN-NEXT: s_bfe_u32 s4, s2, 0x80008
; GCN-NEXT: s_lshr_b32 s2, s2, 16
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: v_sad_u32 v2, s3, v0, v1
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: flat_store_byte v[0:1], v2
; GCN-NEXT: s_endpgm
%icmp0 = icmp ugt i8 %a, %b
Expand Down
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