Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

LSV: document hang reported in #37865 #102479

Merged
merged 3 commits into from
Aug 9, 2024
Merged

Conversation

artagnon
Copy link
Contributor

@artagnon artagnon commented Aug 8, 2024

LoadStoreVectorizer hangs on certain examples, when its reorder function goes into a cycle. Detect this cycle and explicitly forbid it, using an assert, and document the resulting crash in a test-case under AArch64.

LoadStoreVectorizer hangs on certain examples, when its reorder function
goes into a cycle. Detect this cycle and explicitly forbid it, using an
assert, and document the resulting crash in a test-case under AArch64.
@llvmbot
Copy link
Collaborator

llvmbot commented Aug 8, 2024

@llvm/pr-subscribers-llvm-transforms

Author: Ramkumar Ramachandra (artagnon)

Changes

LoadStoreVectorizer hangs on certain examples, when its reorder function goes into a cycle. Detect this cycle and explicitly forbid it, using an assert, and document the resulting crash in a test-case under AArch64.

-- 8< --
It is unclear if this code-path will ever be hit when running the full opt pipeline. Moreover, the fix is also very unclear to me.


Full diff: https://github.com/llvm/llvm-project/pull/102479.diff

2 Files Affected:

  • (modified) llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp (+2)
  • (added) llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll (+13)
diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
index c91911ecad7456..c35ea431296b70 100644
--- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -216,6 +216,8 @@ void reorder(Instruction *I) {
       if (IM->getParent() != I->getParent())
         continue;
 
+      assert(IM != I && "Unexpected cycle while re-ordering instructions");
+
       if (!IM->comesBefore(I)) {
         InstructionsToMove.insert(IM);
         Worklist.push_back(IM);
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
new file mode 100644
index 00000000000000..d77c7256bfadbd
--- /dev/null
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
@@ -0,0 +1,13 @@
+; REQUIRES: asserts
+; RUN: not --crash opt -mtriple=aarch64 -passes=load-store-vectorizer -disable-output %s
+
+define i32 @load_cycle(ptr %x) {
+entry:
+  %gep.x.1 = getelementptr inbounds [2 x i32], ptr %x, i32 0, i32 1
+  %load.x.1 = load i32, ptr %gep.x.1
+  %rem = urem i32 %load.x.1, 1
+  %gep.x.2 = getelementptr inbounds [2 x i32], ptr %x, i32 %rem, i32 0
+  %load.x.2 = load i32, ptr %gep.x.2
+  %ret = add i32 %load.x.2, %load.x.1
+  ret i32 %ret
+}

Copy link
Contributor

@arsenm arsenm left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is unclear if this code-path will ever be hit when running the full opt pipeline.

Doesn't matter? Bugs are bugs? I think this pass is only added by the GPU backends in codegen

Comment on lines +8 to +10
%load.x.1 = load i32, ptr %gep.x.1
%rem = urem i32 %load.x.1, 1
%gep.x.2 = getelementptr inbounds [2 x i32], ptr %x, i32 %rem, i32 0
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think this just failed to check that one of the vectorization pointer candidates actually depends on the other load, so these shouldn't be vectorization candidates

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Right, I figured that I have to fix the creation of the Chain.

@artagnon artagnon merged commit 199d6f2 into llvm:main Aug 9, 2024
8 checks passed
@artagnon artagnon deleted the lsv-37865-test branch August 9, 2024 10:34
@llvm-ci
Copy link
Collaborator

llvm-ci commented Aug 9, 2024

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-sie-win running on sie-win-worker while building llvm at step 7 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/46/builds/2973

Here is the relevant piece of the build log for the reference:

Step 7 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: Transforms/LoadStoreVectorizer/AArch64/pr37865.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
not --crash z:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe -mtriple=aarch64 -passes=load-store-vectorizer    -disable-output Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\test\Transforms\LoadStoreVectorizer\AArch64\pr37865.ll 2>&1 | z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\test\Transforms\LoadStoreVectorizer\AArch64\pr37865.ll
# executed command: not --crash 'z:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe' -mtriple=aarch64 -passes=load-store-vectorizer -disable-output 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\test\Transforms\LoadStoreVectorizer\AArch64\pr37865.ll'
# note: command had no output on stdout or stderr
# error: command failed with exit status: 1
# executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe' 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\test\Transforms\LoadStoreVectorizer\AArch64\pr37865.ll'
# .---command stderr------------
# | �[1mZ:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\test\Transforms\LoadStoreVectorizer\AArch64\pr37865.ll:6:10: �[0m�[0;1;31merror: �[0m�[1mCHECK: expected string not found in input
# | �[0m; CHECK: Unexpected cycle while re-ordering instructions
# | �[0;1;32m         ^
# | �[0m�[1m<stdin>:1:1: �[0m�[0;1;30mnote: �[0m�[1mscanning from here
# | �[0mz:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe: warning: failed to infer data layout: unable to get target for 'aarch64', see --version and --triple.
# | �[0;1;32m^
# | �[0m�[1m<stdin>:2:44: �[0m�[0;1;30mnote: �[0m�[1mpossible intended match here
# | �[0mz:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe: WARNING: failed to create target machine for 'aarch64': unable to get target for 'aarch64', see --version and --triple.
# | �[0;1;32m                                           ^
# | �[0m
# | Input file: <stdin>
# | Check file: Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\test\Transforms\LoadStoreVectorizer\AArch64\pr37865.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# | �[1m�[0m�[0;1;30m           1: �[0m�[1m�[0;1;46mz:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe: warning: failed to infer data layout: unable to get target for 'aarch64', see --version and --triple. �[0m
# | �[0;1;31mcheck:6'0     X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
# | �[0m�[0;1;30m           2: �[0m�[1m�[0;1;46mz:\b\llvm-clang-x86_64-sie-win\build\bin\opt.exe: WARNING: failed to create target machine for 'aarch64': unable to get target for 'aarch64', see --version and --triple. �[0m
# | �[0;1;31mcheck:6'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | �[0m�[0;1;35mcheck:6'1                                                ?                                                                                                                               possible intended match
# | �[0m>>>>>>
# `-----------------------------
# error: command failed with exit status: 1

--

********************


artagnon added a commit to artagnon/llvm-project that referenced this pull request Aug 9, 2024
This reverts commit 199d6f2, as there is a buildbot failure.
@bjope
Copy link
Collaborator

bjope commented Aug 9, 2024

Hi @artagnon,

Downstream we have the fix from https://reviews.llvm.org/D54468, but it seems it never landed upstream.
The new test case you added here fails for us, since we do not trigger the new assert.

When looking at the review comments in https://reviews.llvm.org/D54468 it seems like there were some doubts about the validity of that patch. Nevertheless, we've used that fix downstream for nearly 6 years now.

kutemeikito added a commit to kutemeikito/llvm-project that referenced this pull request Aug 10, 2024
* 'main' of https://github.com/llvm/llvm-project: (700 commits)
  [SandboxIR][NFC] SingleLLVMInstructionImpl class (llvm#102687)
  [ThinLTO]Clean up 'import-assume-unique-local' flag. (llvm#102424)
  [nsan] Make #include more conventional
  [SandboxIR][NFC] Use Tracker.emplaceIfTracking()
  [libc]  Moved range_reduction_double ifdef statement (llvm#102659)
  [libc] Fix CFP long double and add tests (llvm#102660)
  [TargetLowering] Handle vector types in expandFixedPointMul (llvm#102635)
  [compiler-rt][NFC] Replace environment variable with %t (llvm#102197)
  [UnitTests] Convert a test to use opaque pointers (llvm#102668)
  [CodeGen][NFCI] Don't re-implement parts of ASTContext::getIntWidth (llvm#101765)
  [SandboxIR] Clean up tracking code with the help of emplaceIfTracking() (llvm#102406)
  [mlir][bazel] remove extra blanks in mlir-tblgen test
  [NVPTX][NFC] Update tests to use bfloat type (llvm#101493)
  [mlir] Add support for parsing nested PassPipelineOptions (llvm#101118)
  [mlir][bazel] add missing td dependency in mlir-tblgen test
  [flang][cuda] Fix lib dependency
  [libc] Clean up remaining use of *_WIDTH macros in printf (llvm#102679)
  [flang][cuda] Convert cuf.alloc for box to fir.alloca in device context (llvm#102662)
  [SandboxIR] Implement the InsertElementInst class (llvm#102404)
  [libc] Fix use of cpp::numeric_limits<...>::digits (llvm#102674)
  [mlir][ODS] Verify type constraints in Types and Attributes (llvm#102326)
  [LTO] enable `ObjCARCContractPass` only on optimized build  (llvm#101114)
  [mlir][ODS] Consistent `cppType` / `cppClassName` usage (llvm#102657)
  [lldb] Move definition of SBSaveCoreOptions dtor out of header (llvm#102539)
  [libc] Use cpp::numeric_limits in preference to C23 <limits.h> macros (llvm#102665)
  [clang] Implement -fptrauth-auth-traps. (llvm#102417)
  [LLVM][rtsan] rtsan transform to preserve CFGAnalyses (llvm#102651)
  Revert "[AMDGPU] Move `AMDGPUAttributorPass` to full LTO post link stage (llvm#102086)"
  [RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC
  Return available function types for BindingDecls. (llvm#102196)
  [clang] Wire -fptrauth-returns to "ptrauth-returns" fn attribute. (llvm#102416)
  [RISCV] Remove riscv-experimental-rv64-legal-i32. (llvm#102509)
  [RISCV] Move PseudoVSET(I)VLI expansion to use PseudoInstExpansion. (llvm#102496)
  [NVPTX] support switch statement with brx.idx (reland) (llvm#102550)
  [libc][newhdrgen]sorted function names in yaml (llvm#102544)
  [GlobalIsel] Combine G_ADD and G_SUB with constants (llvm#97771)
  Suppress spurious warnings due to R_RISCV_SET_ULEB128
  [scudo] Separated committed and decommitted entries. (llvm#101409)
  [MIPS] Fix missing ANDI optimization (llvm#97689)
  [Clang] Add env var for nvptx-arch/amdgpu-arch timeout (llvm#102521)
  [asan] Switch allocator to dynamic base address (llvm#98511)
  [AMDGPU] Move `AMDGPUAttributorPass` to full LTO post link stage (llvm#102086)
  [libc][math][c23] Add fadd{l,f128} C23 math functions (llvm#102531)
  [mlir][bazel] revert bazel rule change for DLTITransformOps
  [msan] Support vst{2,3,4}_lane instructions (llvm#101215)
  Revert "[MLIR][DLTI][Transform] Introduce transform.dlti.query (llvm#101561)"
  [X86] pr57673.ll - generate MIR test checks
  [mlir][vector][test] Split tests from vector-transfer-flatten.mlir (llvm#102584)
  [mlir][bazel] add bazel rule for DLTITransformOps
  OpenMPOpt: Remove dead include
  [IR] Add method to GlobalVariable to change type of initializer. (llvm#102553)
  [flang][cuda] Force default allocator in device code (llvm#102238)
  [llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (llvm#102578)
  [MLIR][DLTI][Transform] Introduce transform.dlti.query (llvm#101561)
  [AMDGPU][AsmParser][NFC] Remove a misleading comment. (llvm#102604)
  [Arm][AArch64][Clang] Respect function's branch protection attributes. (llvm#101978)
  [mlir] Verifier: steal bit to track seen instead of set. (llvm#102626)
  [Clang] Fix Handling of Init Capture with Parameter Packs in LambdaScopeForCallOperatorInstantiationRAII (llvm#100766)
  [X86] Convert truncsat clamping patterns to use SDPatternMatch. NFC.
  [gn] Give two scripts argparse.RawDescriptionHelpFormatter
  [bazel] Add missing dep for the SPIRVToLLVM target
  [Clang] Simplify specifying passes via -Xoffload-linker (llvm#102483)
  [bazel] Port for d45de80
  [SelectionDAG] Use unaligned store/load to move AVX registers onto stack for `insertelement` (llvm#82130)
  [Clang][OMPX] Add the code generation for multi-dim `num_teams` (llvm#101407)
  [ARM] Regenerate big-endian-vmov.ll. NFC
  [AMDGPU][AsmParser][NFCI] All NamedIntOperands to be of the i32 type. (llvm#102616)
  [libc][math][c23] Add totalorderl function. (llvm#102564)
  [mlir][spirv] Support `memref` in `convert-to-spirv` pass (llvm#102534)
  [MLIR][GPU-LLVM] Convert `gpu.func` to `llvm.func` (llvm#101664)
  Fix a unit test input file (llvm#102567)
  [llvm-readobj][COFF] Dump hybrid objects for ARM64X files. (llvm#102245)
  AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (llvm#102614)
  [MemoryBuiltins] Simplify getCalledFunction() helper (NFC)
  [AArch64] Add invalid 1 x vscale costs for reductions and reduction-operations. (llvm#102105)
  [MemoryBuiltins] Handle allocator attributes on call-site
  LSV/test/AArch64: add missing lit.local.cfg; fix build (llvm#102607)
  Revert "Enable logf128 constant folding for hosts with 128bit floats (llvm#96287)"
  [RISCV] Add Syntacore SCR5 RV32/64 processors definition (llvm#102285)
  [InstCombine] Remove unnecessary RUN line from test (NFC)
  [flang][OpenMP] Handle multiple ranges in `num_teams` clause (llvm#102535)
  [mlir][vector] Add tests for scalable vectors in one-shot-bufferize.mlir (llvm#102361)
  [mlir][vector] Disable `vector.matrix_multiply` for scalable vectors (llvm#102573)
  [clang] Implement CWG2627 Bit-fields and narrowing conversions (llvm#78112)
  [NFC] Use references to avoid copying (llvm#99863)
  Revert "[mlir][ArmSME] Pattern to swap shape_cast(tranpose) with transpose(shape_cast) (llvm#100731)" (llvm#102457)
  [IRBuilder] Generate nuw GEPs for struct member accesses (llvm#99538)
  [bazel] Port for 9b06e25
  [CodeGen][NewPM] Improve start/stop pass error message CodeGenPassBuilder (llvm#102591)
  [AArch64] Implement TRBMPAM_EL1 system register (llvm#102485)
  [InstCombine] Fixing wrong select folding in vectors with undef elements (llvm#102244)
  [AArch64] Sink operands to fmuladd. (llvm#102297)
  LSV: document hang reported in llvm#37865 (llvm#102479)
  Enable logf128 constant folding for hosts with 128bit floats (llvm#96287)
  [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (llvm#102146)
  [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (llvm#102149)
  [mlir][vector] Add mask elimination transform (llvm#99314)
  [Clang][Interp] Fix display of syntactically-invalid note for member function calls (llvm#102170)
  [bazel] Port for 3fffa6d
  [DebugInfo][RemoveDIs] Use iterator-inserters in clang (llvm#102006)
  ...

Signed-off-by: Edwiin Kusuma Jaya <kutemeikito0905@gmail.com>
@artagnon
Copy link
Contributor Author

Hi @bjope,

Yes, I had a look at that patch, but I don't think it's the right fix unfortunately. Will attempt a proper fix in the coming days.

bwendling pushed a commit to bwendling/llvm-project that referenced this pull request Aug 15, 2024
LoadStoreVectorizer hangs on certain examples, when its reorder function
goes into a cycle. Detect this cycle and explicitly forbid it, using an
assert, and document the resulting crash in a test-case under AArch64.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

5 participants