[RISCV][ISel] Move VCIX ISDs to correct position. NFC #105934
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Current VCIX ISDs are placed after FIRST_TARGET_STRICTFP_OPCODE which is not expected, it should be in normal OPCODE area.
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@llvm/pr-subscribers-backend-risc-v Author: Brandon Wu (4vtomat) ChangesCurrent VCIX ISDs are placed after FIRST_TARGET_STRICTFP_OPCODE which is Full diff: https://github.com/llvm/llvm-project/pull/105934.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 2298998b47357d..1b91ab43a4637f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -415,32 +415,6 @@ enum NodeType : unsigned {
/// operand 1 is the target address.
SW_GUARDED_BRIND,
- // FP to 32 bit int conversions for RV64. These are used to keep track of the
- // result being sign extended to 64 bit. These saturate out of range inputs.
- STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE,
- STRICT_FCVT_WU_RV64,
- STRICT_FADD_VL,
- STRICT_FSUB_VL,
- STRICT_FMUL_VL,
- STRICT_FDIV_VL,
- STRICT_FSQRT_VL,
- STRICT_VFMADD_VL,
- STRICT_VFNMADD_VL,
- STRICT_VFMSUB_VL,
- STRICT_VFNMSUB_VL,
- STRICT_FP_ROUND_VL,
- STRICT_FP_EXTEND_VL,
- STRICT_VFNCVT_ROD_VL,
- STRICT_SINT_TO_FP_VL,
- STRICT_UINT_TO_FP_VL,
- STRICT_VFCVT_RM_X_F_VL,
- STRICT_VFCVT_RTZ_X_F_VL,
- STRICT_VFCVT_RTZ_XU_F_VL,
- STRICT_FSETCC_VL,
- STRICT_FSETCCS_VL,
- STRICT_VFROUND_NOEXCEPT_VL,
- LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
-
SF_VC_XV_SE,
SF_VC_IV_SE,
SF_VC_VV_SE,
@@ -468,6 +442,32 @@ enum NodeType : unsigned {
SF_VC_V_VVW_SE,
SF_VC_V_FVW_SE,
+ // FP to 32 bit int conversions for RV64. These are used to keep track of the
+ // result being sign extended to 64 bit. These saturate out of range inputs.
+ STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ STRICT_FCVT_WU_RV64,
+ STRICT_FADD_VL,
+ STRICT_FSUB_VL,
+ STRICT_FMUL_VL,
+ STRICT_FDIV_VL,
+ STRICT_FSQRT_VL,
+ STRICT_VFMADD_VL,
+ STRICT_VFNMADD_VL,
+ STRICT_VFMSUB_VL,
+ STRICT_VFNMSUB_VL,
+ STRICT_FP_ROUND_VL,
+ STRICT_FP_EXTEND_VL,
+ STRICT_VFNCVT_ROD_VL,
+ STRICT_SINT_TO_FP_VL,
+ STRICT_UINT_TO_FP_VL,
+ STRICT_VFCVT_RM_X_F_VL,
+ STRICT_VFCVT_RTZ_X_F_VL,
+ STRICT_VFCVT_RTZ_XU_F_VL,
+ STRICT_FSETCC_VL,
+ STRICT_FSETCCS_VL,
+ STRICT_VFROUND_NOEXCEPT_VL,
+ LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
+
// WARNING: Do not add anything in the end unless you want the node to
// have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
// opcodes will be thought as target memory ops!
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topperc
approved these changes
Aug 24, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/4398 Here is the relevant piece of the build log for the reference: |
dmpolukhin
pushed a commit
to dmpolukhin/llvm-project
that referenced
this pull request
Sep 2, 2024
Current VCIX ISDs are placed after FIRST_TARGET_STRICTFP_OPCODE which is not expected, it should be in normal OPCODE area.
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Current VCIX ISDs are placed after FIRST_TARGET_STRICTFP_OPCODE which is
not expected, it should be in normal OPCODE area.