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update P7 32-bit partial vector load cost #108261

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merged 5 commits into from
Oct 3, 2024
Merged

update P7 32-bit partial vector load cost #108261

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3677531
update P7 v4i8 load cost
RolandF77 Sep 11, 2024
7103010
address comments
RolandF77 Sep 17, 2024
a6bf81b
move decl
RolandF77 Sep 17, 2024
f004e2b
update test
RolandF77 Sep 18, 2024
e44e082
MemBits
RolandF77 Sep 24, 2024
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14 changes: 10 additions & 4 deletions llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -802,12 +802,18 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
// explicitly check this case. There are also corresponding store
// instructions.
unsigned MemBytes = Src->getPrimitiveSizeInBits();
if (ST->hasVSX() && IsAltivecType &&
(MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
return 1;
unsigned SrcBytes = LT.second.getStoreSize();
if (ST->hasVSX() && IsAltivecType) {
if (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))
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@diggerlin diggerlin Sep 18, 2024 •
edited
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nit: this maybe not related to the patch,

I think the variable MemBytes should be MemBits , otherwise it maybe cause mis_understand (it looks like compare with 64bytes and 32bytes)

if (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))

I think we can modify the variable name in the patch by the way?

return 1;

// Use lfiwax/xxspltw
Align AlignBytes = Alignment ? *Alignment : Align(1);
if (Opcode == Instruction::Load && MemBytes == 32 && AlignBytes < SrcBytes)
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I am curious that why need the AlignBytes < SrcBytes here ?

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@RolandF77 RolandF77 Sep 18, 2024 •
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If a partial vector (< 128 bits) is being loaded with a full vector aligned address (>= 128 bits), the load will be done as a full vector load since we know from alignment that it is safe. Therefore the cost of a partial vector load does not apply.

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thanks for explaining.

return 2;
}

// Aligned loads and stores are easy.
unsigned SrcBytes = LT.second.getStoreSize();
if (!SrcBytes || !Alignment || *Alignment >= SrcBytes)
return Cost;

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7 changes: 4 additions & 3 deletions llvm/test/Analysis/CostModel/PowerPC/vsr_load_32_64.ll
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@@ -1,15 +1,16 @@
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck -DCOST32=1 %s
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -DCOST32=2 %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

define i32 @loads(i32 %arg) {
; CHECK: cost of 1 {{.*}} load
; CHECK: cost of [[COST32]] {{.*}} load
load <4 x i8>, ptr undef, align 1

; CHECK: cost of 1 {{.*}} load
load <8 x i8>, ptr undef, align 1

; CHECK: cost of 1 {{.*}} load
; CHECK: cost of [[COST32]] {{.*}} load
load <2 x i16>, ptr undef, align 2

; CHECK: cost of 1 {{.*}} load
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