[NFC][SPIRV] Fix for selectExtInst to be able to process intrinsics #110864
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@llvm/pr-subscribers-backend-spir-v Author: Farzon Lotfi (farzonl) Changes
Full diff: https://github.com/llvm/llvm-project/pull/110864.diff 1 Files Affected:
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 7a565249a342d1..b437217383b5e4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -151,18 +151,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectFCmp(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
- bool selectFmix(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
- bool selectLength(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
- bool selectFrac(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
- bool selectRsqrt(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
bool selectSign(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
@@ -235,18 +223,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectLog10(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
- bool selectNormalize(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
bool selectSaturate(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
- bool selectStep(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
bool selectUnmergeValues(MachineInstr &I) const;
// Utilities
@@ -802,8 +784,12 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
.addImm(static_cast<uint32_t>(Set))
.addImm(Opcode);
const unsigned NumOps = I.getNumOperands();
- for (unsigned i = 1; i < NumOps; ++i)
- MIB.add(I.getOperand(i));
+ unsigned Index = 1;
+ if (I.getOperand(Index).getType() ==
+ MachineOperand::MachineOperandType::MO_IntrinsicID)
+ Index = 2;
+ for (; Index < NumOps; ++Index)
+ MIB.add(I.getOperand(Index));
return MIB.constrainAllUses(TII, TRI, RBI);
}
}
@@ -1605,95 +1591,6 @@ bool SPIRVInstructionSelector::selectAny(Register ResVReg,
return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny);
}
-bool SPIRVInstructionSelector::selectFmix(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 5);
- assert(I.getOperand(2).isReg());
- assert(I.getOperand(3).isReg());
- assert(I.getOperand(4).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::FMix)
- .addUse(I.getOperand(2).getReg())
- .addUse(I.getOperand(3).getReg())
- .addUse(I.getOperand(4).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::selectLength(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 3);
- assert(I.getOperand(2).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::Length)
- .addUse(I.getOperand(2).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::selectFrac(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 3);
- assert(I.getOperand(2).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::Fract)
- .addUse(I.getOperand(2).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::selectNormalize(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 3);
- assert(I.getOperand(2).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::Normalize)
- .addUse(I.getOperand(2).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::selectRsqrt(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 3);
- assert(I.getOperand(2).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::InverseSqrt)
- .addUse(I.getOperand(2).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
// Select the OpDot instruction for the given float dot
bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg,
const SPIRVType *ResType,
@@ -1853,25 +1750,6 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
return Result;
}
-bool SPIRVInstructionSelector::selectStep(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 4);
- assert(I.getOperand(2).isReg());
- assert(I.getOperand(3).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::Step)
- .addUse(I.getOperand(2).getReg())
- .addUse(I.getOperand(3).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
const SPIRVType *ResType,
MachineInstr &I) const {
@@ -2622,15 +2500,15 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::spv_any:
return selectAny(ResVReg, ResType, I);
case Intrinsic::spv_lerp:
- return selectFmix(ResVReg, ResType, I);
+ return selectExtInst(ResVReg, ResType, I, CL::mix, GL::FMix);
case Intrinsic::spv_length:
- return selectLength(ResVReg, ResType, I);
+ return selectExtInst(ResVReg, ResType, I, CL::length, GL::Length);
case Intrinsic::spv_frac:
- return selectFrac(ResVReg, ResType, I);
+ return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
case Intrinsic::spv_normalize:
- return selectNormalize(ResVReg, ResType, I);
+ return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
case Intrinsic::spv_rsqrt:
- return selectRsqrt(ResVReg, ResType, I);
+ return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
case Intrinsic::spv_sign:
return selectSign(ResVReg, ResType, I);
case Intrinsic::spv_lifetime_start:
@@ -2654,7 +2532,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
case Intrinsic::spv_step:
- return selectStep(ResVReg, ResType, I);
+ return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
// Discard intrinsics which we do not expect to actually represent code after
// lowering or intrinsics which are not implemented but should not crash when
// found in a customer's LLVM IR input.
|
python3kgae
approved these changes
Oct 2, 2024
coopp
approved these changes
Oct 2, 2024
Yeah nfc so existing tests not breaking for the intrinsic selects replaced is the test to show this works. |
bogner
approved these changes
Oct 2, 2024
Sterling-Augustine
pushed a commit
to Sterling-Augustine/llvm-project
that referenced
this pull request
Oct 3, 2024
…lvm#110864) `selectExtInst` tries to add the intrinsic to the SPIRV GL extension instruction. `MO_IntrinsicID` is always the first operand when we come from `selectIntrinsic`. For all those cases `selectExtInst` needs to know to start at index 2.
xgupta
pushed a commit
to xgupta/llvm-project
that referenced
this pull request
Oct 4, 2024
…lvm#110864) `selectExtInst` tries to add the intrinsic to the SPIRV GL extension instruction. `MO_IntrinsicID` is always the first operand when we come from `selectIntrinsic`. For all those cases `selectExtInst` needs to know to start at index 2.
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selectExtInsttries to add the intrinsic to the SPIRV GL extension instruction.MO_IntrinsicIDis always the first operand when we come fromselectIntrinsic.For all those cases
selectExtInstneeds to know to start at index 2.