Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[instcombine] Drop zext nneg flag when simplify operand #71088

Merged
merged 2 commits into from
Nov 2, 2023

Conversation

preames
Copy link
Collaborator

@preames preames commented Nov 2, 2023

This fixes a miscompile introduced in the recent #67982, and likely exposed in changes since to infer and leverage the same. No active bug reports as of yet.

This was noticed in #70858 (comment).

This fixes a miscompile introduced in the recent llvm#67982, and likely exposed
in changes since to infer and leverage the same.  No active bug reports as
of yet.

This was noticed in llvm#70858 (comment).
@llvmbot
Copy link
Collaborator

llvmbot commented Nov 2, 2023

@llvm/pr-subscribers-llvm-transforms

Author: Philip Reames (preames)

Changes

This fixes a miscompile introduced in the recent #67982, and likely exposed in changes since to infer and leverage the same. No active bug reports as of yet.

This was noticed in #70858 (comment).


Full diff: https://github.com/llvm/llvm-project/pull/71088.diff

2 Files Affected:

  • (modified) llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (+5-1)
  • (modified) llvm/test/Transforms/InstCombine/zext.ll (+1-1)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index fa6fe9d30abd1b8..30c1565ab44f7a5 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -422,8 +422,12 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
 
     APInt InputDemandedMask = DemandedMask.zextOrTrunc(SrcBitWidth);
     KnownBits InputKnown(SrcBitWidth);
-    if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1))
+    if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1)) {
+      // For zext nneg, we may have dropped the instruction which made the
+      // input non-negative.
+      I->dropPoisonGeneratingFlags();
       return I;
+    }
     assert(InputKnown.getBitWidth() == SrcBitWidth && "Src width changed?");
     Known = InputKnown.zextOrTrunc(BitWidth);
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
diff --git a/llvm/test/Transforms/InstCombine/zext.ll b/llvm/test/Transforms/InstCombine/zext.ll
index 9dd0d929530b333..4034bc3c531b462 100644
--- a/llvm/test/Transforms/InstCombine/zext.ll
+++ b/llvm/test/Transforms/InstCombine/zext.ll
@@ -783,7 +783,7 @@ define i64 @evaluate_zexted_const_expr(i1 %c) {
 ; but the flag on the zext doesn't.
 define i16 @zext_nneg_flag_drop(i8 %x, i16 %y) {
 ; CHECK-LABEL: @zext_nneg_flag_drop(
-; CHECK-NEXT:    [[EXT:%.*]] = zext nneg i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[X:%.*]] to i16
 ; CHECK-NEXT:    [[OR1:%.*]] = or i16 [[EXT]], [[Y:%.*]]
 ; CHECK-NEXT:    [[OR2:%.*]] = or i16 [[OR1]], 128
 ; CHECK-NEXT:    ret i16 [[OR2]]

Copy link
Contributor

@nikic nikic left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@@ -783,7 +783,7 @@ define i64 @evaluate_zexted_const_expr(i1 %c) {
; but the flag on the zext doesn't.
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Drop the FIXME in the line above...

@preames preames merged commit 9593cde into llvm:main Nov 2, 2023
2 of 3 checks passed
@preames preames deleted the pr-instcombine-zext-nneg-miscompile branch November 2, 2023 18:44
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants