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[AArch64] Add the Ampere1B core #81297

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Feb 9, 2024
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[AArch64] Add the Ampere1B core #81297

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1 change: 1 addition & 0 deletions clang/test/Driver/aarch64-cssc.c
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Expand Up @@ -9,6 +9,7 @@
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a %s 2>&1 | FileCheck %s
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+cssc %s 2>&1 | FileCheck %s
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -mcpu=ampere1b %s 2>&1 | FileCheck %s

// CHECK: "target-features"="{{.*}},+cssc
// NO_CSSC: "target-features"="{{.*}},-cssc
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4 changes: 2 additions & 2 deletions clang/test/Misc/target-invalid-cpu-note.c
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Expand Up @@ -5,11 +5,11 @@

// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}

// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}

// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'
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6 changes: 6 additions & 0 deletions llvm/include/llvm/TargetParser/AArch64TargetParser.h
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Expand Up @@ -805,6 +805,12 @@ inline constexpr CpuInfo CpuInfos[] = {
{AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4,
AArch64::AEK_SHA3, AArch64::AEK_SHA2, AArch64::AEK_AES,
AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS}))},
{"ampere1b", ARMV8_7A,
(AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_RAND,
AArch64::AEK_SM4, AArch64::AEK_SHA3,
AArch64::AEK_SHA2, AArch64::AEK_AES,
AArch64::AEK_MTE, AArch64::AEK_SB,
AArch64::AEK_SSBS, AArch64::AEK_CSSC}))},
};

// An alias for a CPU.
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26 changes: 26 additions & 0 deletions llvm/lib/Target/AArch64/AArch64.td
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Expand Up @@ -1376,6 +1376,24 @@ def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
FeatureLdpAlignedOnly,
FeatureStpAlignedOnly]>;

def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B",
"Ampere Computing Ampere-1B processors", [
FeaturePostRAScheduler,
FeatureFuseAES,
FeatureFuseAdrpAdd,
FeatureAddrLSLFast,
FeatureALULSLFast,
FeatureAggressiveFMA,
FeatureArithmeticBccFusion,
FeatureCmpBccFusion,
FeatureFuseAddress,
FeatureFuseLiterals,
FeatureStorePairSuppress,
FeatureEnableSelectOptimize,
FeaturePredictableSelectIsExpensive,
FeatureLdpAlignedOnly,
FeatureStpAlignedOnly]>;

def ProcessorFeatures {
list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
Expand Down Expand Up @@ -1530,6 +1548,11 @@ def ProcessorFeatures {
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES];
list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES, FeatureCSSC,
FeatureWFxT];

// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not
Expand Down Expand Up @@ -1697,6 +1720,9 @@ def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
[TuneAmpere1A]>;

def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
[TuneAmpere1B]>;

//===----------------------------------------------------------------------===//
// Assembly parser
//===----------------------------------------------------------------------===//
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1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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Expand Up @@ -296,6 +296,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
break;
case Ampere1:
case Ampere1A:
case Ampere1B:
CacheLineSize = 64;
PrefFunctionAlignment = Align(64);
PrefLoopAlignment = Align(64);
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1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64Subtarget.h
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Expand Up @@ -42,6 +42,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
A64FX,
Ampere1,
Ampere1A,
Ampere1B,
AppleA7,
AppleA10,
AppleA11,
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1 change: 1 addition & 0 deletions llvm/lib/TargetParser/Host.cpp
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Expand Up @@ -321,6 +321,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
return StringSwitch<const char *>(Part)
.Case("0xac3", "ampere1")
.Case("0xac4", "ampere1a")
.Case("0xac5", "ampere1b")
.Default("generic");
}

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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/cpus.ll
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Expand Up @@ -37,6 +37,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1a 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1b 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID

; CHECK-NOT: {{.*}} is not a recognized processor for this target
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/neon-dot-product.ll
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Expand Up @@ -7,6 +7,7 @@
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1 < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1a < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1b < %s | FileCheck %s

declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/remat.ll
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Expand Up @@ -26,6 +26,7 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1a -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1b -o - %s | FileCheck %s

%X = type { i64, i64, i64 }
declare void @f(ptr)
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3 changes: 3 additions & 0 deletions llvm/test/MC/AArch64/armv8.2a-dotprod.s
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Expand Up @@ -15,6 +15,7 @@
// RUN: llvm-mc -triple aarch64 -mattr=+v8r,+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1a -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1b -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD

// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
Expand Down Expand Up @@ -42,6 +43,8 @@
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1a -mattr=-dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1b -mattr=-dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s

udot v0.2s, v1.8b, v2.8b
sdot v0.2s, v1.8b, v2.8b
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1 change: 1 addition & 0 deletions llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
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Expand Up @@ -14,6 +14,7 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1b --disassemble < %s | FileCheck %s

# CHECK: ldaprb w0, [x0]
# CHECK: ldaprh w0, [x0]
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3 changes: 3 additions & 0 deletions llvm/unittests/TargetParser/Host.cpp
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Expand Up @@ -122,6 +122,9 @@ TEST(getLinuxHostCPUName, AArch64) {
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
"CPU part : 0xac4"),
"ampere1a");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
"CPU part : 0xac5"),
"ampere1b");

// MSM8992/4 weirdness
StringRef MSM8992ProcCpuInfo = R"(
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14 changes: 13 additions & 1 deletion llvm/unittests/TargetParser/TargetParserTest.cpp
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Expand Up @@ -1600,6 +1600,18 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"ampere1b", "armv8.7-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
{AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE,
AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD,
AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM,
AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH, AArch64::AEK_CSSC})),
"8.7-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
Expand Down Expand Up @@ -1679,7 +1691,7 @@ INSTANTIATE_TEST_SUITE_P(
ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName);

// Note: number of CPUs includes aliases.
static constexpr unsigned NumAArch64CPUArchs = 68;
static constexpr unsigned NumAArch64CPUArchs = 69;

TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
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