[Thumb] Resolve FIXME: Use 'mov hi, $src; mov $dst, hi'

[AreaZR]

Consider the following:

    ldr     r0, [r4]
    ldr     r7, [r0, #4]
    cmp     r7, r3
    bhi     .LBB0_6
    cmp     r0, r2
    push    {r0}
    pop     {r4}
    bne     .LBB0_3
    movs    r0, r6
    pop     {r4, r5, r6, r7}
    pop     {r1}
    bx      r1

Here is a snippet of the generated THUMB1 code of the K&R malloc function that clang currently compiles to.

push {r0} ends up being popped to pop {r4}.

movs r4, r0 would destroy the flags set by cmp right above.

The compiler has no alternative in this case, except one:
the only alternative is to transfer through a high register.

However, it seems like LLVM does not consider that this is a valid approach, even though it is a free clobbering a high register.

This patch addresses the FIXME so the compiler can do that when it can in r10 or r11, or r12.

[llvmbot]

@llvm/pr-subscribers-backend-arm

Author: AtariDreams (AtariDreams)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/81908.diff

1 Files Affected:

• (modified) llvm/lib/Target/ARM/Thumb1InstrInfo.cpp (+29-3)

diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 85eabdb17ad190..01b8c76674d207 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -53,9 +53,6 @@ void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
   else {
-    // FIXME: Can also use 'mov hi, $src; mov $dst, hi',
-    // with hi as either r10 or r11.
-
     const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
     if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
         == MachineBasicBlock::LQR_Dead) {
@@ -65,6 +62,35 @@ void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       return;
     }
 
+    // Can also use 'mov hi, $src; mov $dst, hi',
+    // with hi as either r10 or r11.
+    if (MBB.computeRegisterLiveness(RegInfo, ARM::R10, I) ==
+        MachineBasicBlock::LQR_Dead) {
+      // Use high register to move source to destination
+      BuildMI(MBB, I, DL, get(ARM::tMOVr), ARM::R10)
+          .addReg(SrcReg, getKillRegState(KillSrc))
+          .add(predOps(ARMCC::AL));
+      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
+          .addReg(ARM::R10, getKillRegState(KillSrc))
+          .add(predOps(ARMCC::AL))
+          ->addRegisterDead(ARM::R10, RegInfo);
+      return;
+    }
+
+    if (MBB.computeRegisterLiveness(RegInfo, ARM::R11, I) ==
+        MachineBasicBlock::LQR_Dead) {
+      // Use high register to move source to destination
+      BuildMI(MBB, I, DL, get(ARM::tMOVr), ARM::R11)
+          .addReg(SrcReg, getKillRegState(KillSrc))
+          .add(predOps(ARMCC::AL));
+      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
+          .addReg(ARM::R11, getKillRegState(KillSrc))
+          .add(predOps(ARMCC::AL))
+          ->addRegisterDead(ARM::R11, RegInfo);
+      ;
+      return;
+    }
+
     // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
     BuildMI(MBB, I, DL, get(ARM::tPUSH))
         .add(predOps(ARMCC::AL))

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[AreaZR]

@nikic

[AreaZR]

Full source if anyone is curious:

https://godbolt.org/z/h7Pq3s6dM

[efriedma-quic]

(See https://lists.llvm.org/pipermail/llvm-dev/2014-August/075967.html for additional context.)

r10 and r11 are callee-save, so you'd need to make sure they get spilled. We have code to do the spilling, but it's not triggering here. I guess this code runs too late for that to trigger?

[AreaZR]

(See https://lists.llvm.org/pipermail/llvm-dev/2014-August/075967.html for additional context.)

r10 and r11 are callee-save, so you'd need to make sure they get spilled. We have code to do the spilling, but it's not triggering here. I guess this code runs too late for that to trigger?

Pretty sure only r12 is, hence why this is not an option.

[AreaZR]

(See https://lists.llvm.org/pipermail/llvm-dev/2014-August/075967.html for additional context.)

r10 and r11 are callee-save, so you'd need to make sure they get spilled. We have code to do the spilling, but it's not triggering here. I guess this code runs too late for that to trigger?

r10 - Caller save (in ARM mode, unused in Thumb mode)
r11 Caller save (in ARM mode, unused in Thumb mode)

[AreaZR]

r10 and r11 are callee-save, so you'd need to make sure they get spilled

r10 and r11 are callee-save, so you'd need to make sure they get spilled

I only think this is an issue if the compiler were to randomly switch between thumb and arm mode and vice versa mid function, which is a thing that only really happens in handwritten code anyway.

[efriedma-quic]

Pretty sure that's just wrong (or referring to some other calling convention). From the specification (https://github.com/ARM-software/abi-aa/releases):

A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6).

[AreaZR]

@efriedma-quic Okay, I fixed the issues!

[efriedma-quic]

For r10 and r11, as the tests show, they're almost never available; the compiler won't naturally spill them. You can force them to spill using inline asm, but that's so rare it's not really relevant. So I don't really see the point of checking, unless you're planning some sort of followup.

For r12... this is probably okay? We don't use r12 in the scavenger anymore (see ab1d73e). We still use R12 as a scratch register in a few different places, but not in a way that would conflict, I think. It would be helpful if you could take some time to verify that.

If there's some way r12 can actually be live (inline asm?), we should make sure there's at least one test that actually still exercises the code to generate push/pop.

[AreaZR]

@efriedma-quic Ping?

[AreaZR]

@topperc Thoughts?

[TNorthover]

Mostly looks pretty sensible. Couple of comments.

[AreaZR]

@TNorthover Addressed!

[TNorthover]

Thanks. I think this looks good now.