Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[AArch64] Replace AND with LSL#2 for LDR target (#34101) #89531

Merged
merged 2 commits into from
Aug 24, 2024
Merged

[AArch64] Replace AND with LSL#2 for LDR target (#34101) #89531

merged 2 commits into from
Aug 24, 2024
+155 −0

Commits on Aug 21, 2024

  1. [AArch64] Add tests for prevent (shl (srl x, c1), c2) -> (and (shift … 

    …x, c3)) when load
    @ParkHanbum
    ParkHanbum committed Aug 21, 2024
    Configuration menu
    Copy the full SHA
    33d7398 View commit details
    Browse the repository at this point in the history

  2. [AArch64] prevent (shl (srl x, c1), c2) -> (and (shift x, c3)) when load 

    Currently, process of replacing bitwise operations consisting of
`(shl (srl x, c1), c2)` with `And` is performed by `DAGCombiner`.

However, in certain case like `(shl (srl, x, c1) 2)` is do not
need to transform to `AND` if it was used to `Load` Target.

Consider following case:
```
        lsr x8, x8, llvm#56
        and x8, x8, #0xfc
        ldr w0, [x2, x8]
        ret
```

In this case, we can remove the `AND` by changing the target of `LDR`
to `[X2, X8, LSL llvm#2]` and right-shifting amount change to 56 to 58.

after changed:
```
        lsr x8, x8, llvm#58
        ldr w0, [x2, x8, lsl llvm#2]
        ret
```

This patch checks to see if the `(shl (srl x, c1) 2)` operation on
`load` target can be prevent transform to `And`.
    @ParkHanbum
    ParkHanbum committed Aug 21, 2024
    Configuration menu
    Copy the full SHA
    c956250 View commit details
    Browse the repository at this point in the history