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[SDAG] Fix type checks in ShrinkDemandedOp to avoid creating invalid truncates #92730

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[SDAG] Fix type checks in ShrinkDemandedOp to avoid creating invalid truncates #92730

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f57b846
[SDAG] Fix type checks in `ShrinkDemandedOp` to avoid creating invali…
dtcxzyw May 20, 2024
93a276f
[SDAG] Fix bitwidth checks.
dtcxzyw May 20, 2024
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11 changes: 9 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -596,10 +596,17 @@ bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
// Op's type. For expedience, just check power-of-2 integer types.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
unsigned DemandedSize = DemandedBits.getActiveBits();
// Types of LHS and RHS may differ before legalization (e.g., shl), so we
// need to check both.
unsigned MinWidth =
std::min(Op.getOperand(0).getValueType().getScalarSizeInBits(),
Op.getOperand(1).getValueType().getScalarSizeInBits());
for (unsigned SmallVTBits = llvm::bit_ceil(DemandedSize);
SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
SmallVTBits < MinWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
if (TLI.isTruncateFree(VT, SmallVT) && TLI.isZExtFree(SmallVT, VT)) {
if (TLI.isTruncateFree(Op.getOperand(0).getValueType(), SmallVT) &&
TLI.isTruncateFree(Op.getOperand(1).getValueType(), SmallVT) &&
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I'm not sure treating this as the minimum makes sense in the shift case. The RHS type is only an accessory to the main type. It would probably make more sense to stop treating shift as a uniform binary operator, and check the preferred shift amount type for the main type

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See #92753.

TLI.isZExtFree(SmallVT, VT)) {
// We found a type with free casts.
SDValue X = DAG.getNode(
Op.getOpcode(), dl, SmallVT,
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/btc_bts_btr.ll
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Expand Up @@ -1021,7 +1021,7 @@ define i64 @btr_64_mask_zeros(i64 %x, i64 %n) {
; X64-LABEL: btr_64_mask_zeros:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shll $2, %esi
; X64-NEXT: shlq $2, %rsi
; X64-NEXT: btrq %rsi, %rax
; X64-NEXT: retq
;
Expand Down Expand Up @@ -1056,7 +1056,7 @@ define i64 @bts_64_mask_zeros(i64 %x, i64 %n) {
; X64-LABEL: bts_64_mask_zeros:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shll $2, %esi
; X64-NEXT: shlq $2, %rsi
; X64-NEXT: btsq %rsi, %rax
; X64-NEXT: retq
;
Expand Down Expand Up @@ -1088,7 +1088,7 @@ define i64 @btc_64_mask_zeros(i64 %x, i64 %n) {
; X64-LABEL: btc_64_mask_zeros:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shll $2, %esi
; X64-NEXT: shlq $2, %rsi
; X64-NEXT: btcq %rsi, %rax
; X64-NEXT: retq
;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/narrow-shl-cst.ll
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Expand Up @@ -151,7 +151,7 @@ define i32 @test12(i32 %x, ptr %y) nounwind {
define i64 @test13(i64 %x, ptr %y) nounwind {
; CHECK-LABEL: test13:
; CHECK: # %bb.0:
; CHECK-NEXT: addl %edi, %edi
; CHECK-NEXT: addq %rdi, %rdi
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: movq %rax, (%rsi)
; CHECK-NEXT: retq
Expand Down Expand Up @@ -212,7 +212,7 @@ define i64 @test18(i64 %x) nounwind {
; CHECK-LABEL: test18:
; CHECK: # %bb.0:
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: shll $10, %eax
; CHECK-NEXT: shlq $10, %rax
; CHECK-NEXT: retq
%and = shl i64 %x, 10
%shl = and i64 %and, 261120
Expand All @@ -234,7 +234,7 @@ define i64 @test20(i64 %x) nounwind {
; CHECK-LABEL: test20:
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl %di, %eax
; CHECK-NEXT: shll $10, %eax
; CHECK-NEXT: shlq $10, %rax
; CHECK-NEXT: retq
%and = shl i64 %x, 10
%shl = and i64 %and, 67107840
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/pr27202.ll
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Expand Up @@ -45,8 +45,8 @@ define zeroext i1 @g(i32 %x) optsize {
define i64 @PR46237(i64 %x, i64 %y, i64 %z) optsize {
; CHECK-LABEL: PR46237:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll $6, %eax
; CHECK-NEXT: movq %rdx, %rax
; CHECK-NEXT: shlq $6, %rax
; CHECK-NEXT: movzbl %al, %ecx
; CHECK-NEXT: andl $7, %esi
; CHECK-NEXT: andl $7, %edx
Expand Down
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/X86/pr49162.ll
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Expand Up @@ -17,10 +17,7 @@ define ptr @PR49162(ptr %base, ptr %ptr160) {
;
; X64-LABEL: PR49162:
; X64: # %bb.0:
; X64-NEXT: movl 8(%rsi), %eax
; X64-NEXT: shll $16, %eax
; X64-NEXT: cltq
; X64-NEXT: sarq $16, %rax
; X64-NEXT: movswq 8(%rsi), %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq
%load160 = load i160, ptr %ptr160, align 4
Expand Down
15 changes: 15 additions & 0 deletions llvm/test/CodeGen/X86/pr92720.ll
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@@ -0,0 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s

; Make sure we don't crash when shrinking the shift amount before legalization.
define i64 @pr92720(i64 %x) {
; CHECK-LABEL: pr92720:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $8589934592, %rax # imm = 0x200000000
; CHECK-NEXT: retq
%or = or i64 %x, 255
%sub = sub i64 0, %or
%shl = shl i64 1, %sub
%sext = shl i64 %shl, 32
ret i64 %sext
}
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/scheduler-backtracking.ll
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Expand Up @@ -13,7 +13,7 @@ define i256 @test1(i256 %a) nounwind {
; ILP-LABEL: test1:
; ILP: # %bb.0:
; ILP-NEXT: movq %rdi, %rax
; ILP-NEXT: leal (%rsi,%rsi), %ecx
; ILP-NEXT: leaq (%rsi,%rsi), %rcx
; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp)
Expand Down Expand Up @@ -43,7 +43,7 @@ define i256 @test1(i256 %a) nounwind {
; ILP-NEXT: shlq %cl, %rsi
; ILP-NEXT: notb %cl
; ILP-NEXT: shrq %rdx
; ILP-NEXT: # kill: def $cl killed $cl killed $ecx
; ILP-NEXT: # kill: def $cl killed $cl killed $rcx
; ILP-NEXT: shrq %cl, %rdx
; ILP-NEXT: orq %rsi, %rdx
; ILP-NEXT: movq %rdx, 16(%rax)
Expand All @@ -60,7 +60,7 @@ define i256 @test1(i256 %a) nounwind {
; HYBRID-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; HYBRID-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; HYBRID-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; HYBRID-NEXT: addl %esi, %esi
; HYBRID-NEXT: addq %rsi, %rsi
; HYBRID-NEXT: addb $3, %sil
; HYBRID-NEXT: movl %esi, %ecx
; HYBRID-NEXT: andb $7, %cl
Expand Down Expand Up @@ -97,7 +97,7 @@ define i256 @test1(i256 %a) nounwind {
; BURR-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; BURR-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; BURR-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; BURR-NEXT: addl %esi, %esi
; BURR-NEXT: addq %rsi, %rsi
; BURR-NEXT: addb $3, %sil
; BURR-NEXT: movl %esi, %ecx
; BURR-NEXT: andb $7, %cl
Expand Down Expand Up @@ -126,7 +126,7 @@ define i256 @test1(i256 %a) nounwind {
; SRC-LABEL: test1:
; SRC: # %bb.0:
; SRC-NEXT: movq %rdi, %rax
; SRC-NEXT: addl %esi, %esi
; SRC-NEXT: addq %rsi, %rsi
; SRC-NEXT: addb $3, %sil
; SRC-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; SRC-NEXT: movq $0, -{{[0-9]+}}(%rsp)
Expand Down Expand Up @@ -167,7 +167,7 @@ define i256 @test1(i256 %a) nounwind {
; LIN-LABEL: test1:
; LIN: # %bb.0:
; LIN-NEXT: movq %rdi, %rax
; LIN-NEXT: leal (%rsi,%rsi), %edx
; LIN-NEXT: leaq (%rsi,%rsi), %rdx
; LIN-NEXT: addb $3, %dl
; LIN-NEXT: movl %edx, %ecx
; LIN-NEXT: shrb $3, %cl
Expand Down
84 changes: 36 additions & 48 deletions llvm/test/CodeGen/X86/vector-sext.ll
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Expand Up @@ -3615,13 +3615,10 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
; SSE2-NEXT: movd %ecx, %xmm1
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movl 8(%rdi), %ecx
; SSE2-NEXT: shll $28, %ecx
; SSE2-NEXT: movq %rax, %rdx
; SSE2-NEXT: shrq $51, %rdx
; SSE2-NEXT: shll $15, %edx
; SSE2-NEXT: orl %ecx, %edx
; SSE2-NEXT: sarl $15, %edx
; SSE2-NEXT: movd %edx, %xmm1
; SSE2-NEXT: shldq $13, %rax, %rcx
; SSE2-NEXT: shll $15, %ecx
; SSE2-NEXT: sarl $15, %ecx
; SSE2-NEXT: movd %ecx, %xmm1
; SSE2-NEXT: shrq $34, %rax
; SSE2-NEXT: shll $15, %eax
; SSE2-NEXT: sarl $15, %eax
Expand All @@ -3644,13 +3641,10 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
; SSSE3-NEXT: movd %ecx, %xmm1
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-NEXT: movl 8(%rdi), %ecx
; SSSE3-NEXT: shll $28, %ecx
; SSSE3-NEXT: movq %rax, %rdx
; SSSE3-NEXT: shrq $51, %rdx
; SSSE3-NEXT: shll $15, %edx
; SSSE3-NEXT: orl %ecx, %edx
; SSSE3-NEXT: sarl $15, %edx
; SSSE3-NEXT: movd %edx, %xmm1
; SSSE3-NEXT: shldq $13, %rax, %rcx
; SSSE3-NEXT: shll $15, %ecx
; SSSE3-NEXT: sarl $15, %ecx
; SSSE3-NEXT: movd %ecx, %xmm1
; SSSE3-NEXT: shrq $34, %rax
; SSSE3-NEXT: shll $15, %eax
; SSSE3-NEXT: sarl $15, %eax
Expand All @@ -3662,53 +3656,47 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
; SSE41-LABEL: sext_4i17_to_4i32:
; SSE41: # %bb.0:
; SSE41-NEXT: movq (%rdi), %rax
; SSE41-NEXT: movq %rax, %rcx
; SSE41-NEXT: shrq $17, %rcx
; SSE41-NEXT: movl %eax, %ecx
; SSE41-NEXT: movq %rax, %rdx
; SSE41-NEXT: movl 8(%rdi), %esi
; SSE41-NEXT: shldq $13, %rax, %rsi
; SSE41-NEXT: shrq $17, %rax
; SSE41-NEXT: shll $15, %eax
; SSE41-NEXT: sarl $15, %eax
; SSE41-NEXT: shll $15, %ecx
; SSE41-NEXT: sarl $15, %ecx
; SSE41-NEXT: movl %eax, %edx
; SSE41-NEXT: movd %ecx, %xmm0
; SSE41-NEXT: pinsrd $1, %eax, %xmm0
; SSE41-NEXT: shrq $34, %rdx
; SSE41-NEXT: shll $15, %edx
; SSE41-NEXT: sarl $15, %edx
; SSE41-NEXT: movd %edx, %xmm0
; SSE41-NEXT: pinsrd $1, %ecx, %xmm0
; SSE41-NEXT: movq %rax, %rcx
; SSE41-NEXT: shrq $34, %rcx
; SSE41-NEXT: shll $15, %ecx
; SSE41-NEXT: sarl $15, %ecx
; SSE41-NEXT: pinsrd $2, %ecx, %xmm0
; SSE41-NEXT: movl 8(%rdi), %ecx
; SSE41-NEXT: shll $28, %ecx
; SSE41-NEXT: shrq $51, %rax
; SSE41-NEXT: shll $15, %eax
; SSE41-NEXT: orl %ecx, %eax
; SSE41-NEXT: sarl $15, %eax
; SSE41-NEXT: pinsrd $3, %eax, %xmm0
; SSE41-NEXT: pinsrd $2, %edx, %xmm0
; SSE41-NEXT: shll $15, %esi
; SSE41-NEXT: sarl $15, %esi
; SSE41-NEXT: pinsrd $3, %esi, %xmm0
; SSE41-NEXT: retq
;
; AVX-LABEL: sext_4i17_to_4i32:
; AVX: # %bb.0:
; AVX-NEXT: movq (%rdi), %rax
; AVX-NEXT: movq %rax, %rcx
; AVX-NEXT: shrq $17, %rcx
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: movq %rax, %rdx
; AVX-NEXT: movl 8(%rdi), %esi
; AVX-NEXT: shldq $13, %rax, %rsi
; AVX-NEXT: shrq $17, %rax
; AVX-NEXT: shll $15, %eax
; AVX-NEXT: sarl $15, %eax
; AVX-NEXT: shll $15, %ecx
; AVX-NEXT: sarl $15, %ecx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: vmovd %ecx, %xmm0
; AVX-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; AVX-NEXT: shrq $34, %rdx
; AVX-NEXT: shll $15, %edx
; AVX-NEXT: sarl $15, %edx
; AVX-NEXT: vmovd %edx, %xmm0
; AVX-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX-NEXT: movq %rax, %rcx
; AVX-NEXT: shrq $34, %rcx
; AVX-NEXT: shll $15, %ecx
; AVX-NEXT: sarl $15, %ecx
; AVX-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; AVX-NEXT: movl 8(%rdi), %ecx
; AVX-NEXT: shll $28, %ecx
; AVX-NEXT: shrq $51, %rax
; AVX-NEXT: shll $15, %eax
; AVX-NEXT: orl %ecx, %eax
; AVX-NEXT: sarl $15, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
; AVX-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
; AVX-NEXT: shll $15, %esi
; AVX-NEXT: sarl $15, %esi
; AVX-NEXT: vpinsrd $3, %esi, %xmm0, %xmm0
; AVX-NEXT: retq
;
; X86-SSE2-LABEL: sext_4i17_to_4i32:
Expand Down
66 changes: 24 additions & 42 deletions llvm/test/CodeGen/X86/vector-zext.ll
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Expand Up @@ -2332,11 +2332,8 @@ define <4 x i32> @zext_4i17_to_4i32(ptr %ptr) {
; SSE2-NEXT: movd %ecx, %xmm1
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movl 8(%rdi), %ecx
; SSE2-NEXT: shll $13, %ecx
; SSE2-NEXT: movq %rax, %rdx
; SSE2-NEXT: shrq $51, %rdx
; SSE2-NEXT: orl %ecx, %edx
; SSE2-NEXT: movd %edx, %xmm1
; SSE2-NEXT: shldq $13, %rax, %rcx
; SSE2-NEXT: movd %ecx, %xmm1
; SSE2-NEXT: shrq $34, %rax
; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
Expand All @@ -2353,11 +2350,8 @@ define <4 x i32> @zext_4i17_to_4i32(ptr %ptr) {
; SSSE3-NEXT: movd %ecx, %xmm1
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-NEXT: movl 8(%rdi), %ecx
; SSSE3-NEXT: shll $13, %ecx
; SSSE3-NEXT: movq %rax, %rdx
; SSSE3-NEXT: shrq $51, %rdx
; SSSE3-NEXT: orl %ecx, %edx
; SSSE3-NEXT: movd %edx, %xmm1
; SSSE3-NEXT: shldq $13, %rax, %rcx
; SSSE3-NEXT: movd %ecx, %xmm1
; SSSE3-NEXT: shrq $34, %rax
; SSSE3-NEXT: movd %eax, %xmm2
; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
Expand All @@ -2367,15 +2361,12 @@ define <4 x i32> @zext_4i17_to_4i32(ptr %ptr) {
;
; SSE41-LABEL: zext_4i17_to_4i32:
; SSE41: # %bb.0:
; SSE41-NEXT: movl 8(%rdi), %eax
; SSE41-NEXT: shll $13, %eax
; SSE41-NEXT: movq (%rdi), %rcx
; SSE41-NEXT: movq %rcx, %rdx
; SSE41-NEXT: shrq $51, %rdx
; SSE41-NEXT: orl %eax, %edx
; SSE41-NEXT: movq %rcx, %rax
; SSE41-NEXT: movq (%rdi), %rax
; SSE41-NEXT: movd %eax, %xmm0
; SSE41-NEXT: movq %rax, %rcx
; SSE41-NEXT: movl 8(%rdi), %edx
; SSE41-NEXT: shldq $13, %rax, %rdx
; SSE41-NEXT: shrq $17, %rax
; SSE41-NEXT: movd %ecx, %xmm0
; SSE41-NEXT: pinsrd $1, %eax, %xmm0
; SSE41-NEXT: shrq $34, %rcx
; SSE41-NEXT: pinsrd $2, %ecx, %xmm0
Expand All @@ -2385,15 +2376,12 @@ define <4 x i32> @zext_4i17_to_4i32(ptr %ptr) {
;
; AVX1-LABEL: zext_4i17_to_4i32:
; AVX1: # %bb.0:
; AVX1-NEXT: movl 8(%rdi), %eax
; AVX1-NEXT: shll $13, %eax
; AVX1-NEXT: movq (%rdi), %rcx
; AVX1-NEXT: movq %rcx, %rdx
; AVX1-NEXT: shrq $51, %rdx
; AVX1-NEXT: orl %eax, %edx
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: movq (%rdi), %rax
; AVX1-NEXT: vmovd %eax, %xmm0
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: movl 8(%rdi), %edx
; AVX1-NEXT: shldq $13, %rax, %rdx
; AVX1-NEXT: shrq $17, %rax
; AVX1-NEXT: vmovd %ecx, %xmm0
; AVX1-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; AVX1-NEXT: shrq $34, %rcx
; AVX1-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
Expand All @@ -2403,15 +2391,12 @@ define <4 x i32> @zext_4i17_to_4i32(ptr %ptr) {
;
; AVX2-LABEL: zext_4i17_to_4i32:
; AVX2: # %bb.0:
; AVX2-NEXT: movl 8(%rdi), %eax
; AVX2-NEXT: shll $13, %eax
; AVX2-NEXT: movq (%rdi), %rcx
; AVX2-NEXT: movq %rcx, %rdx
; AVX2-NEXT: shrq $51, %rdx
; AVX2-NEXT: orl %eax, %edx
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: movq (%rdi), %rax
; AVX2-NEXT: vmovd %eax, %xmm0
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: movl 8(%rdi), %edx
; AVX2-NEXT: shldq $13, %rax, %rdx
; AVX2-NEXT: shrq $17, %rax
; AVX2-NEXT: vmovd %ecx, %xmm0
; AVX2-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; AVX2-NEXT: shrq $34, %rcx
; AVX2-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
Expand All @@ -2422,15 +2407,12 @@ define <4 x i32> @zext_4i17_to_4i32(ptr %ptr) {
;
; AVX512-LABEL: zext_4i17_to_4i32:
; AVX512: # %bb.0:
; AVX512-NEXT: movl 8(%rdi), %eax
; AVX512-NEXT: shll $13, %eax
; AVX512-NEXT: movq (%rdi), %rcx
; AVX512-NEXT: movq %rcx, %rdx
; AVX512-NEXT: shrq $51, %rdx
; AVX512-NEXT: orl %eax, %edx
; AVX512-NEXT: movq %rcx, %rax
; AVX512-NEXT: movq (%rdi), %rax
; AVX512-NEXT: vmovd %eax, %xmm0
; AVX512-NEXT: movq %rax, %rcx
; AVX512-NEXT: movl 8(%rdi), %edx
; AVX512-NEXT: shldq $13, %rax, %rdx
; AVX512-NEXT: shrq $17, %rax
; AVX512-NEXT: vmovd %ecx, %xmm0
; AVX512-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; AVX512-NEXT: shrq $34, %rcx
; AVX512-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
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