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[DAG][X86] expandABD - add branchless abds/abdu expansion for 0/-1 comparison result cases #92780

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May 23, 2024
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[DAG][X86] expandABD - add branchless abds/abdu expansion for 0/-1 comparison result cases #92780

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14 changes: 12 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9228,11 +9228,21 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
DAG.getNode(ISD::USUBSAT, dl, VT, LHS, RHS),
DAG.getNode(ISD::USUBSAT, dl, VT, RHS, LHS));

// abds(lhs, rhs) -> select(sgt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
// abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
ISD::CondCode CC = IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT;
SDValue Cmp = DAG.getSetCC(dl, CCVT, LHS, RHS, CC);

// Branchless expansion iff cmp result is allbits:
// abds(lhs, rhs) -> sub(sgt(lhs, rhs), xor(sgt(lhs, rhs), sub(lhs, rhs)))
// abdu(lhs, rhs) -> sub(ugt(lhs, rhs), xor(ugt(lhs, rhs), sub(lhs, rhs)))
Comment on lines +9236 to +9237
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I think you need to change either the comparison or the sub to make this work, e.g.:

Suggested change
// abds(lhs, rhs) -> sub(sgt(lhs, rhs), xor(sgt(lhs, rhs), sub(lhs, rhs)))
// abdu(lhs, rhs) -> sub(ugt(lhs, rhs), xor(ugt(lhs, rhs), sub(lhs, rhs)))
// abds(lhs, rhs) -> sub(sgt(lhs, rhs), xor(sgt(lhs, rhs), sub(rhs, lhs)))
// abdu(lhs, rhs) -> sub(ugt(lhs, rhs), xor(ugt(lhs, rhs), sub(rhs, lhs)))

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Alive says no? https://alive2.llvm.org/ce/z/sj863C

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I've double checked with a second abd (max/min) implementation as well: https://alive2.llvm.org/ce/z/wyAMWa

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Yeah, good point, sorry. For some reason I thought the operands of the final sub were the other way round.

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Thanks for checking! OK to commit?

if (CCVT == VT && getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) {
SDValue Diff = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, Diff, Cmp);
return DAG.getNode(ISD::SUB, dl, VT, Cmp, Xor);
}

// abds(lhs, rhs) -> select(sgt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
// abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
return DAG.getSelect(dl, VT, Cmp, DAG.getNode(ISD::SUB, dl, VT, LHS, RHS),
DAG.getNode(ISD::SUB, dl, VT, RHS, LHS));
}
Expand Down
32 changes: 5 additions & 27 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -1108,13 +1108,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
}

setOperationAction(ISD::ABDU, MVT::v16i8, Custom);
setOperationAction(ISD::ABDS, MVT::v16i8, Custom);
setOperationAction(ISD::ABDU, MVT::v8i16, Custom);
setOperationAction(ISD::ABDS, MVT::v8i16, Custom);
setOperationAction(ISD::ABDU, MVT::v4i32, Custom);
setOperationAction(ISD::ABDS, MVT::v4i32, Custom);

setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal);
setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal);
setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
Expand All @@ -1132,9 +1125,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);

for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
setOperationAction(ISD::SETCC, VT, Custom);
setOperationAction(ISD::CTPOP, VT, Custom);
setOperationAction(ISD::ABS, VT, Custom);
setOperationAction(ISD::SETCC, VT, Custom);
setOperationAction(ISD::CTPOP, VT, Custom);
setOperationAction(ISD::ABS, VT, Custom);
setOperationAction(ISD::ABDS, VT, Custom);
setOperationAction(ISD::ABDU, VT, Custom);

// The condition codes aren't legal in SSE/AVX and under AVX512 we use
// setcc all the way to isel and prefer SETGT in some isel patterns.
Expand Down Expand Up @@ -1336,11 +1331,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
setOperationAction(ISD::UMIN, MVT::v4i32, Legal);

for (auto VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) {
setOperationAction(ISD::ABDS, VT, Custom);
setOperationAction(ISD::ABDU, VT, Custom);
}

setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom);
setOperationAction(ISD::SADDSAT, MVT::v2i64, Custom);
setOperationAction(ISD::SSUBSAT, MVT::v2i64, Custom);
Expand Down Expand Up @@ -28421,18 +28411,6 @@ static SDValue LowerABD(SDValue Op, const X86Subtarget &Subtarget,
}
}

// TODO: Move to TargetLowering expandABD().
if (!Subtarget.hasSSE41() &&
((IsSigned && VT == MVT::v16i8) || VT == MVT::v4i32)) {
SDValue LHS = DAG.getFreeze(Op.getOperand(0));
SDValue RHS = DAG.getFreeze(Op.getOperand(1));
ISD::CondCode CC = IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT;
SDValue Cmp = DAG.getSetCC(dl, VT, LHS, RHS, CC);
SDValue Diff0 = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
SDValue Diff1 = DAG.getNode(ISD::SUB, dl, VT, RHS, LHS);
return getBitSelect(dl, VT, Diff0, Diff1, Cmp, DAG);
}

// Default to expand.
return SDValue();
}
Expand Down
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