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Revert "[IR] Avoid creating icmp/fcmp constant expressions" #93087

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May 22, 2024
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Revert "[IR] Avoid creating icmp/fcmp constant expressions" #93087

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36 changes: 17 additions & 19 deletions clang/test/Analysis/builtin_signbit.cpp
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Expand Up @@ -84,30 +84,28 @@ long double ld = -1.0L;
// CHECK-LE-LABEL: define dso_local void @_Z12test_signbitv(
// CHECK-LE-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = icmp slt i64 trunc (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128) to i64), 0
// CHECK-LE-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TMP0]] to i8
// CHECK-LE-NEXT: [[FROMBOOL:%.*]] = zext i1 icmp slt (i64 trunc (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128) to i64), i64 0) to i8
// CHECK-LE-NEXT: store i8 [[FROMBOOL]], ptr @b, align 1
// CHECK-LE-NEXT: [[TMP1:%.*]] = load ppc_fp128, ptr @ld, align 16
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast ppc_fp128 [[TMP1]] to i128
// CHECK-LE-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i64
// CHECK-LE-NEXT: [[TMP4:%.*]] = icmp slt i64 [[TMP3]], 0
// CHECK-LE-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TMP4]] to i8
// CHECK-LE-NEXT: [[TMP0:%.*]] = load ppc_fp128, ptr @ld, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast ppc_fp128 [[TMP0]] to i128
// CHECK-LE-NEXT: [[TMP2:%.*]] = trunc i128 [[TMP1]] to i64
// CHECK-LE-NEXT: [[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
// CHECK-LE-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TMP3]] to i8
// CHECK-LE-NEXT: store i8 [[FROMBOOL1]], ptr @b, align 1
// CHECK-LE-NEXT: store i8 0, ptr @b, align 1
// CHECK-LE-NEXT: [[TMP5:%.*]] = load double, ptr @d, align 8
// CHECK-LE-NEXT: [[CONV:%.*]] = fptrunc double [[TMP5]] to float
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast float [[CONV]] to i32
// CHECK-LE-NEXT: [[TMP7:%.*]] = icmp slt i32 [[TMP6]], 0
// CHECK-LE-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TMP7]] to i8
// CHECK-LE-NEXT: [[TMP4:%.*]] = load double, ptr @d, align 8
// CHECK-LE-NEXT: [[CONV:%.*]] = fptrunc double [[TMP4]] to float
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast float [[CONV]] to i32
// CHECK-LE-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 0
// CHECK-LE-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TMP6]] to i8
// CHECK-LE-NEXT: store i8 [[FROMBOOL2]], ptr @b, align 1
// CHECK-LE-NEXT: [[TMP8:%.*]] = icmp slt i64 trunc (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128) to i64), 0
// CHECK-LE-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TMP8]] to i8
// CHECK-LE-NEXT: [[FROMBOOL3:%.*]] = zext i1 icmp slt (i64 trunc (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128) to i64), i64 0) to i8
// CHECK-LE-NEXT: store i8 [[FROMBOOL3]], ptr @b, align 1
// CHECK-LE-NEXT: [[TMP9:%.*]] = load ppc_fp128, ptr @ld, align 16
// CHECK-LE-NEXT: [[TMP10:%.*]] = bitcast ppc_fp128 [[TMP9]] to i128
// CHECK-LE-NEXT: [[TMP11:%.*]] = trunc i128 [[TMP10]] to i64
// CHECK-LE-NEXT: [[TMP12:%.*]] = icmp slt i64 [[TMP11]], 0
// CHECK-LE-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TMP12]] to i8
// CHECK-LE-NEXT: [[TMP7:%.*]] = load ppc_fp128, ptr @ld, align 16
// CHECK-LE-NEXT: [[TMP8:%.*]] = bitcast ppc_fp128 [[TMP7]] to i128
// CHECK-LE-NEXT: [[TMP9:%.*]] = trunc i128 [[TMP8]] to i64
// CHECK-LE-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], 0
// CHECK-LE-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TMP10]] to i8
// CHECK-LE-NEXT: store i8 [[FROMBOOL4]], ptr @b, align 1
// CHECK-LE-NEXT: ret void
//
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62 changes: 22 additions & 40 deletions clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
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3 changes: 1 addition & 2 deletions clang/test/CodeGen/constantexpr-fneg.c
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Expand Up @@ -8,8 +8,7 @@
// CHECK: entry:
// CHECK-NEXT: %retval = alloca i32
// CHECK-NEXT: store i32 0, ptr %retval
// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a
// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32
// CHECK-NEXT: [[SITOFP:%.*]] = sitofp i32 [[ZEXT]] to float
// CHECK-NEXT: [[LV:%.*]] = load ptr, ptr @c
// CHECK-NEXT: store float [[SITOFP]], ptr [[LV]], align 4
Expand Down
20 changes: 8 additions & 12 deletions clang/test/CodeGenCXX/cxx11-thread-local.cpp
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Expand Up @@ -136,9 +136,8 @@ int f() {
// CHECK-NEXT: store i32 %{{.*}}, ptr @c, align 4

// LINUX_AIX-LABEL: define linkonce_odr hidden noundef ptr @_ZTW1b()
// LINUX: [[CMP:%.*]] = icmp ne ptr @_ZTH1b, null
// LINUX: br i1 [[CMP]]
// AIX-NOT: [[CMP:%.*]] = icmp ne ptr @_ZTH1b, null
// LINUX: br i1 icmp ne (ptr @_ZTH1b, ptr null),
// AIX-NOT: br i1 icmp ne (ptr @_ZTH1b, ptr null),
// not null:
// LINUX_AIX: call void @_ZTH1b()
// LINUX: br label
Expand Down Expand Up @@ -220,27 +219,24 @@ int f() {

// DARWIN: declare cxx_fast_tlscc noundef ptr @_ZTWN1VIcE1mE()
// LINUX_AIX: define linkonce_odr hidden noundef ptr @_ZTWN1VIcE1mE() {{#[0-9]+}}{{( comdat)?}} {
// LINUX: [[CMP:%.*]] = icmp ne ptr @_ZTHN1VIcE1mE,
// LINUX: br i1 [[CMP]]
// AIX-NOT: [[CMP:%.*]] = icmp ne ptr @_ZTHN1VIcE1mE,
// LINUX: br i1 icmp ne (ptr @_ZTHN1VIcE1mE,
// AIX-NOT: br i1 icmp ne (ptr @_ZTHN1VIcE1mE
// LINUX_AIX: call void @_ZTHN1VIcE1mE()
// LINUX_AIX: [[VEM_ADDR:%.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN1VIcE1mE)
// LINUX_AIX: ret ptr [[VEM_ADDR]]

// DARWIN: declare cxx_fast_tlscc noundef ptr @_ZTWN1WIcE1mE()
// LINUX_AIX: define linkonce_odr hidden noundef ptr @_ZTWN1WIcE1mE() {{#[0-9]+}}{{( comdat)?}} {
// LINUX: [[CMP:%.*]] = icmp ne ptr @_ZTHN1WIcE1mE,
// LINUX: br i1 [[CMP]]
// AIX-NOT: [[CMP:%.*]] = icmp ne ptr @_ZTHN1WIcE1mE,
// LINUX: br i1 icmp ne (ptr @_ZTHN1WIcE1mE,
// AIX-NOT: br i1 icmp ne (ptr @_ZTHN1WIcE1mE,
// LINUX_AIX: call void @_ZTHN1WIcE1mE()
// LINUX_AIX: [[WEM_ADDR:%.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN1WIcE1mE)
// LINUX_AIX: ret ptr [[WEM_ADDR]]

// DARWIN: declare cxx_fast_tlscc {{.*}}ptr @_ZTWN1XIcE1mE()
// LINUX_AIX: define linkonce_odr hidden {{.*}}ptr @_ZTWN1XIcE1mE() {{#[0-9]+}}{{( comdat)?}} {
// LINUX: [[CMP:%.*]] = icmp ne ptr @_ZTHN1XIcE1mE,
// LINUX: br i1 [[CMP]]
// AIX-NOT: [[CMP:%.*]] = icmp ne ptr @_ZTHN1XIcE1mE,
// LINUX: br i1 icmp ne (ptr @_ZTHN1XIcE1mE,
// AIX-NOT: br i1 icmp ne (ptr @_ZTHN1XIcE1mE,
// LINUX_AIX: call void @_ZTHN1XIcE1mE()
// LINUX_AIX: [[XEM_ADDR:%.+]] = call align 1 ptr @llvm.threadlocal.address.p0(ptr align 1 @_ZN1XIcE1mE)
// LINUX_AIX: ret ptr [[XEM_ADDR]]
Expand Down
3 changes: 1 addition & 2 deletions clang/test/CodeGenCXX/ubsan-nullability-arg.cpp
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Expand Up @@ -10,8 +10,7 @@ struct S0 {
void foo1(void (S0::*_Nonnull f)());

// ITANIUM-LABEL: @_ZN10method_ptr5test1Ev(){{.*}} {
// ITANIUM: [[CMP:%.*]] = icmp ne i64 ptrtoint (ptr @_ZN10method_ptr2S04foo1Ev to i64), 0
// ITANIUM: br i1 [[CMP]], label %[[CONT:.*]], label %[[FAIL:[^,]*]]
// ITANIUM: br i1 icmp ne (i64 ptrtoint (ptr @_ZN10method_ptr2S04foo1Ev to i64), i64 0), label %[[CONT:.*]], label %[[FAIL:[^,]*]]
// ITANIUM-EMPTY:
// ITANIUM-NEXT: [[FAIL]]:
// ITANIUM-NEXT: call void @__ubsan_handle_nullability_arg
Expand Down
15 changes: 4 additions & 11 deletions clang/test/CodeGenCXX/weak-external.cpp
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Expand Up @@ -80,30 +80,23 @@ namespace not_weak_on_first {
namespace constant_eval {
[[gnu::weak]] extern int a;
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
// CHECK: [[CMP:%.*]] = icmp ne ptr @_ZN13constant_eval1aE, null
// CHECK: [[ZEXT:%.*]] = zext i1 [[CMP]] to i8
// CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (ptr @_ZN13constant_eval1aE, ptr null) to i8
// CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_a1E,
bool has_a1 = &a;
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
// CHECK: [[CMP:%.*]] = icmp ne ptr @_ZN13constant_eval1aE, null
// CHECK: [[ZEXT:%.*]] = zext i1 [[CMP]] to i8
// CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (ptr @_ZN13constant_eval1aE, ptr null) to i8
// CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_a2E,
bool has_a2 = &a != nullptr;

struct X {
[[gnu::weak]] void f();
};
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
// CHECK: [[CMP:%.*]] = icmp ne i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), 0
// CHECK: [[ZEXT:%.*]] = zext i1 [[CMP]] to i8
// CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), i{{32|64}} 0) to i8
// CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_f1E,
bool has_f1 = &X::f;
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
// CHECK: [[CMP:%.*]] = icmp ne i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), 0
// CHECK: [[CMP2:%.*]] = icmp ne i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), 0
// CHECK: [[AND:%.*]] = and i1 [[CMP2]], false
// CHECK: [[OR:%.*]] = or i1 [[CMP]], [[AND]]
// CHECK: [[ZEXT:%.*]] = zext i1 [[OR]] to i8
// CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), i{{32|64}} 0) to i8
// CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_f2E,
bool has_f2 = &X::f != nullptr;
}
98 changes: 48 additions & 50 deletions clang/test/Driver/linker-wrapper-image.c
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Expand Up @@ -83,33 +83,32 @@

// CUDA: define internal void @.cuda.globals_reg(ptr %0) section ".text.startup" {
// CUDA-NEXT: entry:
// CUDA-NEXT: %1 = icmp ne ptr @__start_cuda_offloading_entries, @__stop_cuda_offloading_entries
// CUDA-NEXT: br i1 %1, label %while.entry, label %while.end
// CUDA-NEXT: br i1 icmp ne (ptr @__start_cuda_offloading_entries, ptr @__stop_cuda_offloading_entries), label %while.entry, label %while.end

// CUDA: while.entry:
// CUDA-NEXT: %entry1 = phi ptr [ @__start_cuda_offloading_entries, %entry ], [ %12, %if.end ]
// CUDA-NEXT: %2 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 0
// CUDA-NEXT: %addr = load ptr, ptr %2, align 8
// CUDA-NEXT: %3 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 1
// CUDA-NEXT: %name = load ptr, ptr %3, align 8
// CUDA-NEXT: %4 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 2
// CUDA-NEXT: %size = load i64, ptr %4, align 4
// CUDA-NEXT: %5 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 3
// CUDA-NEXT: %flags = load i32, ptr %5, align 4
// CUDA-NEXT: %6 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 4
// CUDA-NEXT: %textype = load i32, ptr %6, align 4
// CUDA-NEXT: %entry1 = phi ptr [ @__start_cuda_offloading_entries, %entry ], [ %11, %if.end ]
// CUDA-NEXT: %1 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 0
// CUDA-NEXT: %addr = load ptr, ptr %1, align 8
// CUDA-NEXT: %2 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 1
// CUDA-NEXT: %name = load ptr, ptr %2, align 8
// CUDA-NEXT: %3 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 2
// CUDA-NEXT: %size = load i64, ptr %3, align 4
// CUDA-NEXT: %4 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 3
// CUDA-NEXT: %flags = load i32, ptr %4, align 4
// CUDA-NEXT: %5 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 4
// CUDA-NEXT: %textype = load i32, ptr %5, align 4
// CUDA-NEXT: %type = and i32 %flags, 7
// CUDA-NEXT: %7 = and i32 %flags, 8
// CUDA-NEXT: %extern = lshr i32 %7, 3
// CUDA-NEXT: %8 = and i32 %flags, 16
// CUDA-NEXT: %constant = lshr i32 %8, 4
// CUDA-NEXT: %9 = and i32 %flags, 32
// CUDA-NEXT: %normalized = lshr i32 %9, 5
// CUDA-NEXT: %10 = icmp eq i64 %size, 0
// CUDA-NEXT: br i1 %10, label %if.then, label %if.else
// CUDA-NEXT: %6 = and i32 %flags, 8
// CUDA-NEXT: %extern = lshr i32 %6, 3
// CUDA-NEXT: %7 = and i32 %flags, 16
// CUDA-NEXT: %constant = lshr i32 %7, 4
// CUDA-NEXT: %8 = and i32 %flags, 32
// CUDA-NEXT: %normalized = lshr i32 %8, 5
// CUDA-NEXT: %9 = icmp eq i64 %size, 0
// CUDA-NEXT: br i1 %9, label %if.then, label %if.else

// CUDA: if.then:
// CUDA-NEXT: %11 = call i32 @__cudaRegisterFunction(ptr %0, ptr %addr, ptr %name, ptr %name, i32 -1, ptr null, ptr null, ptr null, ptr null, ptr null)
// CUDA-NEXT: %10 = call i32 @__cudaRegisterFunction(ptr %0, ptr %addr, ptr %name, ptr %name, i32 -1, ptr null, ptr null, ptr null, ptr null, ptr null)
// CUDA-NEXT: br label %if.end

// CUDA: if.else:
Expand All @@ -134,9 +133,9 @@
// CUDA-NEXT: br label %if.end

// CUDA: if.end:
// CUDA-NEXT: %12 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 1
// CUDA-NEXT: %13 = icmp eq ptr %12, @__stop_cuda_offloading_entries
// CUDA-NEXT: br i1 %13, label %while.end, label %while.entry
// CUDA-NEXT: %11 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 1
// CUDA-NEXT: %12 = icmp eq ptr %11, @__stop_cuda_offloading_entries
// CUDA-NEXT: br i1 %12, label %while.end, label %while.entry

// CUDA: while.end:
// CUDA-NEXT: ret void
Expand Down Expand Up @@ -183,33 +182,32 @@

// HIP: define internal void @.hip.globals_reg(ptr %0) section ".text.startup" {
// HIP-NEXT: entry:
// HIP-NEXT: %1 = icmp ne ptr @__start_hip_offloading_entries, @__stop_hip_offloading_entries
// HIP-NEXT: br i1 %1, label %while.entry, label %while.end
// HIP-NEXT: br i1 icmp ne (ptr @__start_hip_offloading_entries, ptr @__stop_hip_offloading_entries), label %while.entry, label %while.end

// HIP: while.entry:
// HIP-NEXT: %entry1 = phi ptr [ @__start_hip_offloading_entries, %entry ], [ %12, %if.end ]
// HIP-NEXT: %2 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 0
// HIP-NEXT: %addr = load ptr, ptr %2, align 8
// HIP-NEXT: %3 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 1
// HIP-NEXT: %name = load ptr, ptr %3, align 8
// HIP-NEXT: %4 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 2
// HIP-NEXT: %size = load i64, ptr %4, align 4
// HIP-NEXT: %5 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 3
// HIP-NEXT: %flags = load i32, ptr %5, align 4
// HIP-NEXT: %6 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 4
// HIP-NEXT: %textype = load i32, ptr %6, align 4
// HIP-NEXT: %entry1 = phi ptr [ @__start_hip_offloading_entries, %entry ], [ %11, %if.end ]
// HIP-NEXT: %1 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 0
// HIP-NEXT: %addr = load ptr, ptr %1, align 8
// HIP-NEXT: %2 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 1
// HIP-NEXT: %name = load ptr, ptr %2, align 8
// HIP-NEXT: %3 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 2
// HIP-NEXT: %size = load i64, ptr %3, align 4
// HIP-NEXT: %4 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 3
// HIP-NEXT: %flags = load i32, ptr %4, align 4
// HIP-NEXT: %5 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 0, i32 4
// HIP-NEXT: %textype = load i32, ptr %5, align 4
// HIP-NEXT: %type = and i32 %flags, 7
// HIP-NEXT: %7 = and i32 %flags, 8
// HIP-NEXT: %extern = lshr i32 %7, 3
// HIP-NEXT: %8 = and i32 %flags, 16
// HIP-NEXT: %constant = lshr i32 %8, 4
// HIP-NEXT: %9 = and i32 %flags, 32
// HIP-NEXT: %normalized = lshr i32 %9, 5
// HIP-NEXT: %10 = icmp eq i64 %size, 0
// HIP-NEXT: br i1 %10, label %if.then, label %if.else
// HIP-NEXT: %6 = and i32 %flags, 8
// HIP-NEXT: %extern = lshr i32 %6, 3
// HIP-NEXT: %7 = and i32 %flags, 16
// HIP-NEXT: %constant = lshr i32 %7, 4
// HIP-NEXT: %8 = and i32 %flags, 32
// HIP-NEXT: %normalized = lshr i32 %8, 5
// HIP-NEXT: %9 = icmp eq i64 %size, 0
// HIP-NEXT: br i1 %9, label %if.then, label %if.else

// HIP: if.then:
// HIP-NEXT: %11 = call i32 @__hipRegisterFunction(ptr %0, ptr %addr, ptr %name, ptr %name, i32 -1, ptr null, ptr null, ptr null, ptr null, ptr null)
// HIP-NEXT: %10 = call i32 @__hipRegisterFunction(ptr %0, ptr %addr, ptr %name, ptr %name, i32 -1, ptr null, ptr null, ptr null, ptr null, ptr null)
// HIP-NEXT: br label %if.end

// HIP: if.else:
Expand All @@ -236,9 +234,9 @@
// HIP-NEXT: br label %if.end

// HIP: if.end:
// HIP-NEXT: %12 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 1
// HIP-NEXT: %13 = icmp eq ptr %12, @__stop_hip_offloading_entries
// HIP-NEXT: br i1 %13, label %while.end, label %while.entry
// HIP-NEXT: %11 = getelementptr inbounds %struct.__tgt_offload_entry, ptr %entry1, i64 1
// HIP-NEXT: %12 = icmp eq ptr %11, @__stop_hip_offloading_entries
// HIP-NEXT: br i1 %12, label %while.end, label %while.entry

// HIP: while.end:
// HIP-NEXT: ret void
Expand Down
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