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[RISCV][InsertVSETVLI] Eliminate the AVLIsIgnored state #94658

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merged 2 commits into from
Jun 17, 2024
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[RISCV][InsertVSETVLI] Eliminate the AVLIsIgnored state #94658

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e9a68c9
[RISCV][InsertVSETVLI] Eliminate the AVLIsIgnored state
preames Jun 6, 2024
cdabb91
Merge branch 'main' into pr-insertvsetvli-kill-avl-ignored
preames Jun 17, 2024
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57 changes: 10 additions & 47 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -397,7 +397,9 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
if (RISCVII::hasSEWOp(TSFlags)) {
Res.demandVTYPE();
if (RISCVII::hasVLOp(TSFlags))
Res.demandVL();
if (const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
!VLOp.isReg() || !VLOp.isUndef())
Res.demandVL();

// Behavior is independent of mask policy.
if (!RISCVII::usesMaskPolicy(TSFlags))
Expand Down Expand Up @@ -517,7 +519,6 @@ class VSETVLIInfo {
AVLIsReg,
AVLIsImm,
AVLIsVLMAX,
AVLIsIgnored,
Unknown,
} State = Uninitialized;

Expand Down Expand Up @@ -557,12 +558,9 @@ class VSETVLIInfo {

void setAVLVLMAX() { State = AVLIsVLMAX; }

void setAVLIgnored() { State = AVLIsIgnored; }

bool hasAVLImm() const { return State == AVLIsImm; }
bool hasAVLReg() const { return State == AVLIsReg; }
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
Register getAVLReg() const {
assert(hasAVLReg() && AVLRegDef.DefReg.isVirtual());
return AVLRegDef.DefReg;
Expand Down Expand Up @@ -593,8 +591,6 @@ class VSETVLIInfo {
setAVLRegDef(Info.getAVLVNInfo(), Info.getAVLReg());
else if (Info.hasAVLVLMAX())
setAVLVLMAX();
else if (Info.hasAVLIgnored())
setAVLIgnored();
else {
assert(Info.hasAVLImm());
setAVLImm(Info.getAVLImm());
Expand All @@ -615,8 +611,6 @@ class VSETVLIInfo {
}
if (hasAVLVLMAX())
return true;
if (hasAVLIgnored())
return false;
return false;
}

Expand All @@ -638,9 +632,6 @@ class VSETVLIInfo {
if (hasAVLVLMAX())
return Other.hasAVLVLMAX() && hasSameVLMAX(Other);

if (hasAVLIgnored())
return Other.hasAVLIgnored();

return false;
}

Expand Down Expand Up @@ -816,8 +807,6 @@ class VSETVLIInfo {
OS << "AVLImm=" << (unsigned)AVLImm;
if (hasAVLVLMAX())
OS << "AVLVLMAX";
if (hasAVLIgnored())
OS << "AVLIgnored";
OS << ", "
<< "VLMul=" << (unsigned)VLMul << ", "
<< "SEW=" << (unsigned)SEW << ", "
Expand Down Expand Up @@ -936,7 +925,8 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const {
NewInfo.setAVLRegDef(VNI, AVLReg);
else {
assert(MI.getOperand(1).isUndef());
NewInfo.setAVLIgnored();
// Otherwise use an AVL of 1 to avoid depending on previous vl.
NewInfo.setAVLImm(1);
}
}
NewInfo.setVTYPE(MI.getOperand(2).getImm());
Expand Down Expand Up @@ -1012,14 +1002,14 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const {
InstrInfo.setAVLRegDef(VNI, VLOp.getReg());
} else {
assert(VLOp.isUndef());
InstrInfo.setAVLIgnored();
// Otherwise use an AVL of 1 to avoid depending on previous vl.
InstrInfo.setAVLImm(1);
}
} else {
assert(isScalarExtractInstr(MI));
// TODO: If we are more clever about x0,x0 insertion then we should be able
// to deduce that the VL is ignored based off of DemandedFields, and remove
// the AVLIsIgnored state. Then we can just use an arbitrary immediate AVL.
InstrInfo.setAVLIgnored();
// Pick a random value for state tracking purposes, will be ignored via
// the demanded fields mechanism
InstrInfo.setAVLImm(1);
}
#ifndef NDEBUG
if (std::optional<unsigned> EEW = getEEWForLoadStore(MI)) {
Expand Down Expand Up @@ -1099,28 +1089,6 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
return;
}

if (Info.hasAVLIgnored()) {
// We can only use x0, x0 if there's no chance of the vtype change causing
// the previous vl to become invalid.
if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
Info.hasSameVLMAX(PrevInfo)) {
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE())
.addReg(RISCV::VL, RegState::Implicit);
LIS->InsertMachineInstrInMaps(*MI);
return;
}
// Otherwise use an AVL of 1 to avoid depending on previous vl.
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addImm(1)
.addImm(Info.encodeVTYPE());
LIS->InsertMachineInstrInMaps(*MI);
return;
}

if (Info.hasAVLVLMAX()) {
Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
Expand Down Expand Up @@ -1529,11 +1497,6 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
return;
}

// If the AVL isn't used in its predecessors then bail, since we have no AVL
// to insert a vsetvli with.
if (AvailableInfo.hasAVLIgnored())
return;

// Model the effect of changing the input state of the block MBB to
// AvailableInfo. We're looking for two issues here; one legality,
// one profitability.
Expand Down
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