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[flang] Fixing PPC lit failure due to alloca reordering. #95621

Merged
merged 7 commits into from
Jun 14, 2024
Merged

[flang] Fixing PPC lit failure due to alloca reordering. #95621

merged 7 commits into from
Jun 14, 2024

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VijayKandiah
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This change fixes the PowerPC lit tests that are failing due to the recent change to hoist constant-sized allocas at flang codegen. Three of these changed lit tests are entirely rewritten to use variables instead of numbered LLVM IR.

@llvmbot llvmbot added flang Flang issues not falling into any other category flang:fir-hlfir labels Jun 14, 2024
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llvmbot commented Jun 14, 2024

@llvm/pr-subscribers-flang-fir-hlfir

Author: Vijay Kandiah (VijayKandiah)

Changes

This change fixes the PowerPC lit tests that are failing due to the recent change to hoist constant-sized allocas at flang codegen. Three of these changed lit tests are entirely rewritten to use variables instead of numbered LLVM IR.

Patch is 249.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/95621.diff

5 Files Affected:

  • (modified) flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90 (+381-380)
  • (modified) flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90 (+756-756)
  • (modified) flang/test/Lower/PowerPC/ppc-mma-outer-product-2.f90 (+377-377)
  • (modified) flang/test/Lower/PowerPC/ppc-pwr10-vec-intrinsics.f90 (+4-4)
  • (modified) flang/test/Lower/PowerPC/ppc-vector-types.f90 (+4-4)
diff --git a/flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90 b/flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90
index d3872891853d4..17603535760bb 100644
--- a/flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90
+++ b/flang/test/Lower/PowerPC/ppc-mma-assemble-disassemble.f90
@@ -12,17 +12,18 @@ subroutine test_assemble_acc_i1()
       end subroutine test_assemble_acc_i1
 
 ! CHECK-LABEL: @test_assemble_acc_i1
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %3 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %4 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %5 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %6 = load <16 x i8>, ptr %2, align 16
-! LLVMIR:  %7 = load <16 x i8>, ptr %3, align 16
-! LLVMIR:  %8 = load <16 x i8>, ptr %4, align 16
-! LLVMIR:  %9 = load <16 x i8>, ptr %5, align 16
-! LLVMIR:  %10 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %6, <16 x i8> %7, <16 x i8> %8, <16 x i8> %9)
-! LLVMIR:  store <512 x i1> %10, ptr %1, align 64
+
+! LLVMIR:         %[[VAL_0:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_1:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_2:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_3:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_4:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_5:.*]] = load <16 x i8>, ptr %[[VAL_3]], align 16
+! LLVMIR:         %[[VAL_6:.*]] = load <16 x i8>, ptr %[[VAL_2]], align 16
+! LLVMIR:         %[[VAL_7:.*]] = load <16 x i8>, ptr %[[VAL_1]], align 16
+! LLVMIR:         %[[VAL_8:.*]] = load <16 x i8>, ptr %[[VAL_0]], align 16
+! LLVMIR:         %[[VAL_9:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_5]], <16 x i8> %[[VAL_6]], <16 x i8> %[[VAL_7]], <16 x i8> %[[VAL_8]])
+! LLVMIR:         store <512 x i1> %[[VAL_9]], ptr %[[VAL_4]], align 64
 
       subroutine test_assemble_acc_i2()
       use, intrinsic :: mma
@@ -33,21 +34,21 @@ subroutine test_assemble_acc_i2()
       end subroutine test_assemble_acc_i2
 
 ! CHECK-LABEL: @test_assemble_acc_i2
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %3 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %4 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %5 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %6 = load <8 x i16>, ptr %2, align 16
-! LLVMIR:  %7 = load <8 x i16>, ptr %3, align 16
-! LLVMIR:  %8 = load <8 x i16>, ptr %4, align 16
-! LLVMIR:  %9 = load <8 x i16>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <8 x i16> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <8 x i16> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <8 x i16> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <8 x i16> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_10:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_11:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_12:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_13:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_14:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_15:.*]] = load <8 x i16>, ptr %[[VAL_13]], align 16
+! LLVMIR:         %[[VAL_16:.*]] = load <8 x i16>, ptr %[[VAL_12]], align 16
+! LLVMIR:         %[[VAL_17:.*]] = load <8 x i16>, ptr %[[VAL_11]], align 16
+! LLVMIR:         %[[VAL_18:.*]] = load <8 x i16>, ptr %[[VAL_10]], align 16
+! LLVMIR:         %[[VAL_19:.*]] = bitcast <8 x i16> %[[VAL_15]] to <16 x i8>
+! LLVMIR:         %[[VAL_20:.*]] = bitcast <8 x i16> %[[VAL_16]] to <16 x i8>
+! LLVMIR:         %[[VAL_21:.*]] = bitcast <8 x i16> %[[VAL_17]] to <16 x i8>
+! LLVMIR:         %[[VAL_22:.*]] = bitcast <8 x i16> %[[VAL_18]] to <16 x i8>
+! LLVMIR:         %[[VAL_23:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_19]], <16 x i8> %[[VAL_20]], <16 x i8> %[[VAL_21]], <16 x i8> %[[VAL_22]])
+! LLVMIR:         store <512 x i1> %[[VAL_23]], ptr %[[VAL_14]], align 64
 
 
       subroutine test_assemble_acc_i4()
@@ -59,21 +60,21 @@ subroutine test_assemble_acc_i4()
       end subroutine test_assemble_acc_i4
 
 ! CHECK-LABEL: @test_assemble_acc_i4
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %3 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %4 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %5 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %6 = load <4 x i32>, ptr %2, align 16
-! LLVMIR:  %7 = load <4 x i32>, ptr %3, align 16
-! LLVMIR:  %8 = load <4 x i32>, ptr %4, align 16
-! LLVMIR:  %9 = load <4 x i32>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <4 x i32> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <4 x i32> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <4 x i32> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <4 x i32> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_24:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_25:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_26:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_27:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_28:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_29:.*]] = load <4 x i32>, ptr %[[VAL_27]], align 16
+! LLVMIR:         %[[VAL_30:.*]] = load <4 x i32>, ptr %[[VAL_26]], align 16
+! LLVMIR:         %[[VAL_31:.*]] = load <4 x i32>, ptr %[[VAL_25]], align 16
+! LLVMIR:         %[[VAL_32:.*]] = load <4 x i32>, ptr %[[VAL_24]], align 16
+! LLVMIR:         %[[VAL_33:.*]] = bitcast <4 x i32> %[[VAL_29]] to <16 x i8>
+! LLVMIR:         %[[VAL_34:.*]] = bitcast <4 x i32> %[[VAL_30]] to <16 x i8>
+! LLVMIR:         %[[VAL_35:.*]] = bitcast <4 x i32> %[[VAL_31]] to <16 x i8>
+! LLVMIR:         %[[VAL_36:.*]] = bitcast <4 x i32> %[[VAL_32]] to <16 x i8>
+! LLVMIR:         %[[VAL_37:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_33]], <16 x i8> %[[VAL_34]], <16 x i8> %[[VAL_35]], <16 x i8> %[[VAL_36]])
+! LLVMIR:         store <512 x i1> %[[VAL_37]], ptr %[[VAL_28]], align 64
 
       subroutine test_assemble_acc_i8()
       use, intrinsic :: mma
@@ -84,21 +85,21 @@ subroutine test_assemble_acc_i8()
       end subroutine test_assemble_acc_i8
 
 ! CHECK-LABEL: @test_assemble_acc_i8
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %3 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %4 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %5 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %6 = load <2 x i64>, ptr %2, align 16
-! LLVMIR:  %7 = load <2 x i64>, ptr %3, align 16
-! LLVMIR:  %8 = load <2 x i64>, ptr %4, align 16
-! LLVMIR:  %9 = load <2 x i64>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <2 x i64> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <2 x i64> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <2 x i64> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <2 x i64> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_38:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_39:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_40:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_41:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_42:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_43:.*]] = load <2 x i64>, ptr %[[VAL_41]], align 16
+! LLVMIR:         %[[VAL_44:.*]] = load <2 x i64>, ptr %[[VAL_40]], align 16
+! LLVMIR:         %[[VAL_45:.*]] = load <2 x i64>, ptr %[[VAL_39]], align 16
+! LLVMIR:         %[[VAL_46:.*]] = load <2 x i64>, ptr %[[VAL_38]], align 16
+! LLVMIR:         %[[VAL_47:.*]] = bitcast <2 x i64> %[[VAL_43]] to <16 x i8>
+! LLVMIR:         %[[VAL_48:.*]] = bitcast <2 x i64> %[[VAL_44]] to <16 x i8>
+! LLVMIR:         %[[VAL_49:.*]] = bitcast <2 x i64> %[[VAL_45]] to <16 x i8>
+! LLVMIR:         %[[VAL_50:.*]] = bitcast <2 x i64> %[[VAL_46]] to <16 x i8>
+! LLVMIR:         %[[VAL_51:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_47]], <16 x i8> %[[VAL_48]], <16 x i8> %[[VAL_49]], <16 x i8> %[[VAL_50]])
+! LLVMIR:         store <512 x i1> %[[VAL_51]], ptr %[[VAL_42]], align 64
 
 
       subroutine test_assemble_acc_u1()
@@ -110,17 +111,17 @@ subroutine test_assemble_acc_u1()
       end subroutine test_assemble_acc_u1
 
 ! CHECK-LABEL: @test_assemble_acc_u1
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %3 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %4 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %5 = alloca <16 x i8>, i64 1, align 16
-! LLVMIR:  %6 = load <16 x i8>, ptr %2, align 16
-! LLVMIR:  %7 = load <16 x i8>, ptr %3, align 16
-! LLVMIR:  %8 = load <16 x i8>, ptr %4, align 16
-! LLVMIR:  %9 = load <16 x i8>, ptr %5, align 16
-! LLVMIR:  %10 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %6, <16 x i8> %7, <16 x i8> %8, <16 x i8> %9)
-! LLVMIR:  store <512 x i1> %10, ptr %1, align 64
+! LLVMIR:         %[[VAL_52:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_53:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_54:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_55:.*]] = alloca <16 x i8>, i64 1, align 16
+! LLVMIR:         %[[VAL_56:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_57:.*]] = load <16 x i8>, ptr %[[VAL_55]], align 16
+! LLVMIR:         %[[VAL_58:.*]] = load <16 x i8>, ptr %[[VAL_54]], align 16
+! LLVMIR:         %[[VAL_59:.*]] = load <16 x i8>, ptr %[[VAL_53]], align 16
+! LLVMIR:         %[[VAL_60:.*]] = load <16 x i8>, ptr %[[VAL_52]], align 16
+! LLVMIR:         %[[VAL_61:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_57]], <16 x i8> %[[VAL_58]], <16 x i8> %[[VAL_59]], <16 x i8> %[[VAL_60]])
+! LLVMIR:         store <512 x i1> %[[VAL_61]], ptr %[[VAL_56]], align 64
 
       subroutine test_assemble_acc_u2()
       use, intrinsic :: mma
@@ -131,21 +132,21 @@ subroutine test_assemble_acc_u2()
       end subroutine test_assemble_acc_u2
 
 ! CHECK-LABEL: @test_assemble_acc_u2
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %3 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %4 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %5 = alloca <8 x i16>, i64 1, align 16
-! LLVMIR:  %6 = load <8 x i16>, ptr %2, align 16
-! LLVMIR:  %7 = load <8 x i16>, ptr %3, align 16
-! LLVMIR:  %8 = load <8 x i16>, ptr %4, align 16
-! LLVMIR:  %9 = load <8 x i16>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <8 x i16> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <8 x i16> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <8 x i16> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <8 x i16> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_62:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_63:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_64:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_65:.*]] = alloca <8 x i16>, i64 1, align 16
+! LLVMIR:         %[[VAL_66:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_67:.*]] = load <8 x i16>, ptr %[[VAL_65]], align 16
+! LLVMIR:         %[[VAL_68:.*]] = load <8 x i16>, ptr %[[VAL_64]], align 16
+! LLVMIR:         %[[VAL_69:.*]] = load <8 x i16>, ptr %[[VAL_63]], align 16
+! LLVMIR:         %[[VAL_70:.*]] = load <8 x i16>, ptr %[[VAL_62]], align 16
+! LLVMIR:         %[[VAL_71:.*]] = bitcast <8 x i16> %[[VAL_67]] to <16 x i8>
+! LLVMIR:         %[[VAL_72:.*]] = bitcast <8 x i16> %[[VAL_68]] to <16 x i8>
+! LLVMIR:         %[[VAL_73:.*]] = bitcast <8 x i16> %[[VAL_69]] to <16 x i8>
+! LLVMIR:         %[[VAL_74:.*]] = bitcast <8 x i16> %[[VAL_70]] to <16 x i8>
+! LLVMIR:         %[[VAL_75:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_71]], <16 x i8> %[[VAL_72]], <16 x i8> %[[VAL_73]], <16 x i8> %[[VAL_74]])
+! LLVMIR:         store <512 x i1> %[[VAL_75]], ptr %[[VAL_66]], align 64
 
       subroutine test_assemble_acc_u4()
       use, intrinsic :: mma
@@ -156,21 +157,21 @@ subroutine test_assemble_acc_u4()
       end subroutine test_assemble_acc_u4
 
 ! CHECK-LABEL: @test_assemble_acc_u4
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %3 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %4 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %5 = alloca <4 x i32>, i64 1, align 16
-! LLVMIR:  %6 = load <4 x i32>, ptr %2, align 16
-! LLVMIR:  %7 = load <4 x i32>, ptr %3, align 16
-! LLVMIR:  %8 = load <4 x i32>, ptr %4, align 16
-! LLVMIR:  %9 = load <4 x i32>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <4 x i32> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <4 x i32> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <4 x i32> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <4 x i32> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_76:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_77:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_78:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_79:.*]] = alloca <4 x i32>, i64 1, align 16
+! LLVMIR:         %[[VAL_80:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_81:.*]] = load <4 x i32>, ptr %[[VAL_79]], align 16
+! LLVMIR:         %[[VAL_82:.*]] = load <4 x i32>, ptr %[[VAL_78]], align 16
+! LLVMIR:         %[[VAL_83:.*]] = load <4 x i32>, ptr %[[VAL_77]], align 16
+! LLVMIR:         %[[VAL_84:.*]] = load <4 x i32>, ptr %[[VAL_76]], align 16
+! LLVMIR:         %[[VAL_85:.*]] = bitcast <4 x i32> %[[VAL_81]] to <16 x i8>
+! LLVMIR:         %[[VAL_86:.*]] = bitcast <4 x i32> %[[VAL_82]] to <16 x i8>
+! LLVMIR:         %[[VAL_87:.*]] = bitcast <4 x i32> %[[VAL_83]] to <16 x i8>
+! LLVMIR:         %[[VAL_88:.*]] = bitcast <4 x i32> %[[VAL_84]] to <16 x i8>
+! LLVMIR:         %[[VAL_89:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_85]], <16 x i8> %[[VAL_86]], <16 x i8> %[[VAL_87]], <16 x i8> %[[VAL_88]])
+! LLVMIR:         store <512 x i1> %[[VAL_89]], ptr %[[VAL_80]], align 64
 
       subroutine test_assemble_acc_u8()
       use, intrinsic :: mma
@@ -181,21 +182,21 @@ subroutine test_assemble_acc_u8()
       end subroutine test_assemble_acc_u8
 
 ! CHECK-LABEL: @test_assemble_acc_u8
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %3 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %4 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %5 = alloca <2 x i64>, i64 1, align 16
-! LLVMIR:  %6 = load <2 x i64>, ptr %2, align 16
-! LLVMIR:  %7 = load <2 x i64>, ptr %3, align 16
-! LLVMIR:  %8 = load <2 x i64>, ptr %4, align 16
-! LLVMIR:  %9 = load <2 x i64>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <2 x i64> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <2 x i64> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <2 x i64> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <2 x i64> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_90:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_91:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_92:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_93:.*]] = alloca <2 x i64>, i64 1, align 16
+! LLVMIR:         %[[VAL_94:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_95:.*]] = load <2 x i64>, ptr %[[VAL_93]], align 16
+! LLVMIR:         %[[VAL_96:.*]] = load <2 x i64>, ptr %[[VAL_92]], align 16
+! LLVMIR:         %[[VAL_97:.*]] = load <2 x i64>, ptr %[[VAL_91]], align 16
+! LLVMIR:         %[[VAL_98:.*]] = load <2 x i64>, ptr %[[VAL_90]], align 16
+! LLVMIR:         %[[VAL_99:.*]] = bitcast <2 x i64> %[[VAL_95]] to <16 x i8>
+! LLVMIR:         %[[VAL_100:.*]] = bitcast <2 x i64> %[[VAL_96]] to <16 x i8>
+! LLVMIR:         %[[VAL_101:.*]] = bitcast <2 x i64> %[[VAL_97]] to <16 x i8>
+! LLVMIR:         %[[VAL_102:.*]] = bitcast <2 x i64> %[[VAL_98]] to <16 x i8>
+! LLVMIR:         %[[VAL_103:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_99]], <16 x i8> %[[VAL_100]], <16 x i8> %[[VAL_101]], <16 x i8> %[[VAL_102]])
+! LLVMIR:         store <512 x i1> %[[VAL_103]], ptr %[[VAL_94]], align 64
 
       subroutine test_assemble_acc_r4()
       use, intrinsic :: mma
@@ -206,21 +207,21 @@ subroutine test_assemble_acc_r4()
       end subroutine test_assemble_acc_r4
 
 ! CHECK-LABEL: @test_assemble_acc_r4
-! LLVMIR:  %1 = alloca <512 x i1>, i64 1, align 64
-! LLVMIR:  %2 = alloca <4 x float>, i64 1, align 16
-! LLVMIR:  %3 = alloca <4 x float>, i64 1, align 16
-! LLVMIR:  %4 = alloca <4 x float>, i64 1, align 16
-! LLVMIR:  %5 = alloca <4 x float>, i64 1, align 16
-! LLVMIR:  %6 = load <4 x float>, ptr %2, align 16
-! LLVMIR:  %7 = load <4 x float>, ptr %3, align 16
-! LLVMIR:  %8 = load <4 x float>, ptr %4, align 16
-! LLVMIR:  %9 = load <4 x float>, ptr %5, align 16
-! LLVMIR:  %10 = bitcast <4 x float> %6 to <16 x i8>
-! LLVMIR:  %11 = bitcast <4 x float> %7 to <16 x i8>
-! LLVMIR:  %12 = bitcast <4 x float> %8 to <16 x i8>
-! LLVMIR:  %13 = bitcast <4 x float> %9 to <16 x i8>
-! LLVMIR:  %14 = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %10, <16 x i8> %11, <16 x i8> %12, <16 x i8> %13)
-! LLVMIR:  store <512 x i1> %14, ptr %1, align 64
+! LLVMIR:         %[[VAL_104:.*]] = alloca <4 x float>, i64 1, align 16
+! LLVMIR:         %[[VAL_105:.*]] = alloca <4 x float>, i64 1, align 16
+! LLVMIR:         %[[VAL_106:.*]] = alloca <4 x float>, i64 1, align 16
+! LLVMIR:         %[[VAL_107:.*]] = alloca <4 x float>, i64 1, align 16
+! LLVMIR:         %[[VAL_108:.*]] = alloca <512 x i1>, i64 1, align 64
+! LLVMIR:         %[[VAL_109:.*]] = load <4 x float>, ptr %[[VAL_107]], align 16
+! LLVMIR:         %[[VAL_110:.*]] = load <4 x float>, ptr %[[VAL_106]], align 16
+! LLVMIR:         %[[VAL_111:.*]] = load <4 x float>, ptr %[[VAL_105]], align 16
+! LLVMIR:         %[[VAL_112:.*]] = load <4 x float>, ptr %[[VAL_104]], align 16
+! LLVMIR:         %[[VAL_113:.*]] = bitcast <4 x float> %[[VAL_109]] to <16 x i8>
+! LLVMIR:         %[[VAL_114:.*]] = bitcast <4 x float> %[[VAL_110]] to <16 x i8>
+! LLVMIR:         %[[VAL_115:.*]] = bitcast <4 x float> %[[VAL_111]] to <16 x i8>
+! LLVMIR:         %[[VAL_116:.*]] = bitcast <4 x float> %[[VAL_112]] to <16 x i8>
+! LLVMIR:         %[[VAL_117:.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %[[VAL_113]], <16 x i8> %[[VAL_114]], <16 x i8> %[[VAL_115]], <16 x i8> %[[VAL_116]])
+! LLVMIR:         store <512 x i1> %[[VAL_117]], ptr %[[VAL_108]], align 64
 
       subroutine test_assemble_acc_r8()
       use, intrinsic :: mma
@@ -231,21 +232,21 @@ subroutine test_assemble_acc_r8()
       end subroutine test_assemble_acc_r8
 
 !CHECK-LABEL: @test_assemble_acc_r8
-!LLVMIR:   %1 = alloca <512 x i1>, i64 1, align 64
-!LLVMIR:   %2 = alloca <2 x double>, i64 1, align 16
-!LLVMIR:   %3 = alloca <2 x double>, i64 1, align 16
-!LLVMIR:   %4 = alloca <2 x double>, i64 1, align 16
-!LLVMIR:   %5 = alloca <2 x double>, i64 1, align 16
-!LLVMIR:   %6 = load <2 x double>, ptr %2, align 16
-!LLVMIR:   %7 = load <2 x double>, ptr %3, align 16
-!LLVMIR:   %8 = load <2 x double>, ptr %4, align 16
-!LLVMIR:   %9 = load <2 x double>, ptr %5, align 16
-!LLVMIR:   %10 = bitcast <2 x double> %6 to <16 x i8>
-!LLVMIR:   %11 = bitcast <2 x double> %7 to <16 x i8>
-!LLVMIR:   %12 = bitcast <2 x double> %8 to <16 x i8>
...
[truncated]

clementval
clementval approved these changes Jun 14, 2024
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LGTM. Someone from the ppc contributors should get rid of the hardcoded ssa values

flang/test/Lower/PowerPC/ppc-pwr10-vec-intrinsics.f90
@@ -28,9 +28,9 @@ end subroutine test_cvspbf16
!CHECK-LABEL: @test_cvspbf16_
!LLVMIR: %1 = alloca <16 x i8>, i64 1, align 16
!LLVMIR: %2 = alloca <16 x i8>, i64 1, align 16
!LLVMIR: %3 = load <16 x i8>, ptr %2, align 16
!LLVMIR: %3 = load <16 x i8>, ptr %1, align 16
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Not you fault but these tests should not use hardcoded ssa value

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I agree, these tests need to be rewritten to not use hardcoded ssa values.

@VijayKandiah VijayKandiah merged commit daac13f into llvm:main Jun 14, 2024
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@jpienaar jpienaar mentioned this pull request Jun 17, 2024
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@clementval clementval clementval approved these changes

@vzakhari vzakhari Awaiting requested review from vzakhari

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@VijayKandiah @llvmbot @clementval