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[MachineLICM] Correctly Apply Register Masks #95746

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merged 3 commits into from
Jun 17, 2024
Merged

[MachineLICM] Correctly Apply Register Masks #95746

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63224bb
[MachineLICM] Fix regression introduced by d4b8b72
Pierre-vh Jun 17, 2024
1b848f8
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Pierre-vh Jun 17, 2024
e3f3dae
skip empty words + add fixme
Pierre-vh Jun 17, 2024
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22 changes: 7 additions & 15 deletions llvm/lib/CodeGen/MachineLICM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -426,9 +426,7 @@ static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
BitVector &RUs,
const uint32_t *Mask) {
const unsigned NumRUs = TRI.getNumRegUnits();
BitVector RUsInMask(NumRUs);
BitVector RUsNotInMask(NumRUs);
BitVector ClobberedRUs(TRI.getNumRegUnits(), true);
const unsigned NumRegs = TRI.getNumRegs();
const unsigned MaskWords = (NumRegs + 31) / 32;
for (unsigned K = 0; K < MaskWords; ++K) {
Expand All @@ -438,21 +436,15 @@ static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
if (PhysReg == NumRegs)
break;

if (!PhysReg)
continue;

// Extract the bit and apply it to the appropriate mask.
auto &Mask = ((Word >> Bit) & 1) ? RUsInMask : RUsNotInMask;
for (MCRegUnitIterator RUI(PhysReg, &TRI); RUI.isValid(); ++RUI)
Mask.set(*RUI);
// Check if we have a valid PhysReg that is set in the mask.
if (PhysReg && ((Word >> Bit) & 1)) {
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for (MCRegUnitIterator RUI(PhysReg, &TRI); RUI.isValid(); ++RUI)
ClobberedRUs.reset(*RUI);
}
}
}

// If a RU needs to be set because it's not in the RegMask, only set it
// if all registers from that RU are not in the mask either.
RUsNotInMask &= RUsInMask.flip();

RUs |= RUsNotInMask;
RUs |= ClobberedRUs;
}

/// Examine the instruction for potentai LICM candidate. Also
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