Allow literal bvs to be used under conditionals

[lsrcz]

This pull request allows the following code to work:

symIte "cond" 1 2 :: SomeSymWordN

The result will be in the state where the bit width is undetermined. It will be assigned a bit width when further used with other bit vectors that have a bit width.

[codecov]

Codecov Report

Attention: Patch coverage is 31.29771% with 90 lines in your changes missing coverage. Please review.

Project coverage is 54.66%. Comparing base (9413cac) to head (6d6c1d7).
Report is 3 commits behind head on main.

Files with missing lines	Patch %	Lines
src/Grisette/Internal/SymPrim/SomeBV.hs	31.29%	89 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main     #261      +/-   ##
==========================================
- Coverage   54.94%   54.66%   -0.28%     
==========================================
  Files         121      121              
  Lines       12806    12914     +108     
  Branches      906      908       +2     
==========================================
+ Hits         7036     7060      +24     
- Misses       4864     4946      +82     
- Partials      906      908       +2     

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