[RISCV] Fix vmerge.vvm/vmv.v.v getting folded into ops with mismatchi…

…ng EEW

As noted in https://github.com/llvm/llvm-project/pull/100367/files#r1695448771, we currently fold in vmerge.vvms and vmv.v.vs into their ops even if the EEW is different. This is incorrect if we end up changing the mask or AVL of the op.

This gets the op's EEW via its simple value type for now since there doesn't seem to be any existing information about the EEW size of instructions. We'll probably need to encode this at some point if we want to be able to access it at the MachineInstr level in llvm#100367

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3855,11 +3855,19 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
   // If we end up changing the VL or mask of True, then we need to make sure it
   // doesn't raise any observable fp exceptions, since changing the active
   // elements will affect how fflags is set.
-  if (TrueVL != VL || !IsMasked)
+  if (TrueVL != VL || !IsMasked) {
     if (mayRaiseFPException(True.getNode()) &&
         !True->getFlags().hasNoFPExcept())
       return false;
 
+    // If the EEW of True is different from vmerge's SEW, then we cannot change
+    // the VL or mask.
+    if (Log2_64(True.getSimpleValueType().getScalarSizeInBits()) !=
+        N->getConstantOperandVal(
+            RISCVII::getSEWOpNum(TII->get(N->getMachineOpcode())) - 1))
+      return false;
+  }
+
   SDLoc DL(N);
 
   // From the preconditions we checked above, we know the mask and thus glue

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

@@ -1200,8 +1200,10 @@ define <vscale x 2 x i32> @true_mask_vmerge_implicit_passthru(<vscale x 2 x i32>
 define <vscale x 2 x i32> @unfoldable_mismatched_sew_mask(<vscale x 2 x i32> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, <vscale x 2 x i1> %mask, i64 %avl) {
 ; CHECK-LABEL: unfoldable_mismatched_sew_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu
-; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
 ; CHECK-NEXT:    ret
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, i64 %avl)
   %a.bitcast = bitcast <vscale x 1 x i64> %a to <vscale x 2 x i32>
@@ -1218,8 +1220,10 @@ define <vscale x 2 x i32> @unfoldable_mismatched_sew_mask(<vscale x 2 x i32> %pa
 define <vscale x 2 x i32> @unfoldable_mismatched_sew_avl(<vscale x 2 x i32> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y) {
 ; CHECK-LABEL: unfoldable_mismatched_sew_avl:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 3, e64, m1, tu, ma
-; CHECK-NEXT:    vadd.vv v8, v9, v10
+; CHECK-NEXT:    vsetivli zero, 5, e64, m1, ta, ma
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, tu, ma
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, i64 5)
   %a.bitcast = bitcast <vscale x 1 x i64> %a to <vscale x 2 x i32>

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll

@@ -184,8 +184,10 @@ define <vscale x 2 x i32> @unfoldable_vredsum(<vscale x 2 x i32> %passthru, <vsc
 define <vscale x 2 x i32> @unfoldable_mismatched_sew_diff_vl(<vscale x 2 x i32> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y) {
 ; CHECK-LABEL: unfoldable_mismatched_sew_diff_vl:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 3, e64, m1, tu, ma
-; CHECK-NEXT:    vadd.vv v8, v9, v10
+; CHECK-NEXT:    vsetivli zero, 6, e64, m1, ta, ma
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, tu, ma
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen 6)
   %a.bitcast = bitcast <vscale x 1 x i64> %a to <vscale x 2 x i32>