test_ad9910: don't expect large SYNC_IN delay margins

sinara-hw/Urukul#16 Signed-off-by: Robert Jördens <rj@quartiq.de>
m-labs · Nov 7, 2018 · fcb611d · fcb611d
1 parent e6efe83
commit fcb611d
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/artiq/test/coredevice/test_ad9910.py b/artiq/test/coredevice/test_ad9910.py
@@ -82,7 +82,9 @@ def sync_window(self):
             print(err)
             self.core.break_realtime()
         dly, win = self.dev.tune_sync_delay()
-        self.sync_scan(err, win=win + 1)  # tighten window by 2*75ps
+        self.sync_scan(err, win=win)
+        # FIXME: win + 1  # tighten window by 2*75ps
+        # after https://github.com/sinara-hw/Urukul/issues/16
         self.set_dataset("dly", dly)
         self.set_dataset("win", win)
         self.set_dataset("err", err)