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DRTIO #562

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jordens opened this issue Sep 26, 2016 · 12 comments
Closed

DRTIO #562

jordens opened this issue Sep 26, 2016 · 12 comments
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@jordens
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jordens commented Sep 26, 2016

DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central master device.

https://github.com/m-labs/artiq/wiki/DRTIO

@sbourdeauducq
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Funded by Oxford (without switch support)

@jbqubit
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jbqubit commented Jan 26, 2017

What is the development checklist for DRTIO? How is is progressing?

@jordens
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jordens commented Jan 26, 2017

@jbqubit
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jbqubit commented Jan 26, 2017

​The scope of DRTIO/DMA funded by Oxford remains obscure to me. ARL is also funding a big chunk of the distributed DMA. It would be helpful to know what subset of the features discussed in the wiki are expected under these combined contracts. My expectation based on past practice is a checklist. For example,

#580
#561

Thoughts @hartytp?

@sbourdeauducq
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@jbqubit As far as your contract goes, everything is in place for phase 2 except changing the frequency to match the DAC and more annoyingly fixing the obscure packet corruption bug (There is the sysref sync as well but this is not DRTIO). Also, this issue is not the best place for your message.

@sbourdeauducq
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Packet corruption bug fixed.

@sbourdeauducq
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@cjbe Basic DRTIO with outputs only works at 1.25Gbps with commit 9501d37. You can have a look if you want.

@sbourdeauducq
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sbourdeauducq commented Feb 25, 2017

Remaining steps:

  • moninj
  • get the Xilinx Transceiver Garbage to work over 1.25Gbps (>= 3Gbps as per Oxford contract)
  • multiple satellites on one master (needs XTG support)
  • inputs
  • replace/collision
  • busy

@sbourdeauducq
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Remote moninj working

@sbourdeauducq
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There are still problems with:

  • link initialization that fails intermittently, seems XTG-related so I will not spend time looking into it, maybe this just won't happen on GTH/Sinara.
  • data rates other than 1.25Gbps, definitely XTG-related.
  • core.reset() that causes spurious reports of satellite-side underflows, sequence errors and collisions, seems to be a logic bug.

Other than that, DRTIO systems with 2 boards (the master having local RTIO in addition to the satellite connection) have pretty much everything.

@sbourdeauducq sbourdeauducq added this to the 4.0 milestone Oct 1, 2017
@sbourdeauducq sbourdeauducq modified the milestones: 4.0, 5.0 Jan 11, 2018
@dnadlinger
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Anything else missing from this umbrella bug?

@sbourdeauducq
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No.

@sbourdeauducq sbourdeauducq modified the milestones: 5.0, 4.0 Jun 30, 2018
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