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DRTIO #562
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Funded by Oxford (without switch support) |
What is the development checklist for DRTIO? How is is progressing? |
The scope of DRTIO/DMA funded by Oxford remains obscure to me. ARL is also funding a big chunk of the distributed DMA. It would be helpful to know what subset of the features discussed in the wiki are expected under these combined contracts. My expectation based on past practice is a checklist. For example, Thoughts @hartytp? |
@jbqubit As far as your contract goes, everything is in place for phase 2 except changing the frequency to match the DAC and more annoyingly fixing the obscure packet corruption bug (There is the sysref sync as well but this is not DRTIO). Also, this issue is not the best place for your message. |
Packet corruption bug fixed. |
Remaining steps:
|
Remote moninj working |
There are still problems with:
Other than that, DRTIO systems with 2 boards (the master having local RTIO in addition to the satellite connection) have pretty much everything. |
Anything else missing from this umbrella bug? |
No. |
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central master device.
https://github.com/m-labs/artiq/wiki/DRTIO
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