Sinara board support: m-labs

[jbqubit]

What are steps to enable ARTIQ support for Sinara hardware? As of 7/24/2017 topics for this Issue are now tracked via the following milestones.

4.0 mile stones -- Sayma baseline support
https://github.com/m-labs/artiq/milestone/11

5.0 mile stones -- extended Sayma support
https://github.com/m-labs/artiq/milestone/14

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Sinara board support

White paper on clocking of Sinara hardware is here.

ARTIQ v3

Many features of ARTIQ v3 are required for Sayma. Tracking for ARTIQ v3 is here.

• DRTIO ARTIQ #562
  • bare-bones demonstration of clock and data recovery using pair of KC705: transceiver test
  • depends on DMA ARTIQ #553 and ARTIQ wiki

ICs and configuration common to Sinara hardware

ICs common to several boards in the Sinara family follow.

• monitoring/reset/LEDs (also available for WUT via IPMI)
  • I2C_MUX
  • LM75AIMM/NOPB I2C temperature monitors
  • MAX6642ATT90 temperature sensor
• Si5324 Precision Clock Multiplier/Jitter Attenuator
• MAX24287ETK+ Ethernet interface
• FT4232H Quad High Speed USB to Multipurpose UART/MPSSE IC
• LPC1776 hard-core ARM uP --- not supported by m-labs
• SATA pinout SATA pinout unification #157

Kintex Ultrascale related

This is XCKU040 FPGA. Sinara tracking of this is #3; primary tracking is ARTIQ #563.

Metlino

PCB_metlino

• LPC17762984 used for IPMI (ignored by m-labs)
• VHDCI support exposes IO that mimics Kasli peripheral interface Sinara FMC and VHDCI support #148
• RTM support exposes IO, clk in ARTIQ for future uses -- not supported in v0.1
• FMC configuration as in Sinara FMC and VHDCI support #148
• transceiver allocation for SFP/SATA/FAT_PIPE as in SFP/SATA/FAT_PIPE usage #149

Sayma

Software/gateware support for Sayma consists of the following parts.

phaser (analog output)

• AD9154 DAC
• jesd204b link to DAC on KC705
• jesd204b dds demo ARTIQ #580
• two-tone demo with kc705+ad9154 ARTIQ #561
• dsp/gateware features phaser2 features #2

ingester (analog input)

Analog input is not supported in m-labs support for v0.1.

• AD9656 ADC -- not yet funded
• jesd204b input
• jesd204b support for AD9656
• basic servo (PID-like) wiki

PCB_sayma_AMC

• LPC17762984 used for IPMI (ignored by m-labs)
• FMC configuration as in Sinara FMC and VHDCI support #148

PCB_sayma_RTM

• clock distribution (summarized here)
  • HMC7043 SPI 14-Output Fanout Buffer for JESD204B
  • HMC830 SPI fractional-N PLL
• AD7194BCPZ analog mezzanine monitoring/calibration ADC specify analog mezzanine monitoring/calibration ADC functionality #141
• monitoring/reset/LEDs (also available for WUT via IPMI)
  • PCF8574ADW 8-Bit I/O Expander for I2C-Bus
  • 24LC64-I/MS EEPROM
• Sayma RTM/AMC FPGA link Sayma AMC-RTM FPGA link #140

PCB_mezzanine_analog_allaki

ARTIQ support is summarized in leading post in #144. High level:

• The AMC-RTM FPGA link is needed. Sayma AMC-RTM FPGA link #140
• At a high level the users interacts with the analog mezzanines using TTL PHY and SPI PHY.
• "Someone has to look up where each pin is connected, dig into datasheets, write nice Python functions that wiggle them, write device database entries, test everything, go through a few rounds of yak shaving, write documentation, etc."

[jbqubit]

Support needed for AD7194BCPZ analog mezzanine monitoring/calibration ADC established in Issue #141.

[jbqubit]

@jordens @sbourdeauducq Please propose a road map for support of Sayma v0.1 hardware with emphasis on the LogiQ use case. Please include testing, delegation and responsibilities.

[jbqubit]

M-Labs hasn't made their own roadmap or checklist for Sayma support in the ARTIQ repository. I'd like to keep this open so I can roughly track what the steps are.

[sbourdeauducq]

Take our quote SINARA2 and the earlier UMD one - it's in there. Why do you want it in the ARTIQ repository?

[jbqubit]

A subset of the Sayma-dependencies is funded by ARL/UMD with the balance funded by Oxford. Other groups with an interest in Sayma don't have access to the contracts that fund the gateware/software work so are unaware about what's forthcoming. My previous efforts to introspect M-Labs development plans and make lists (eg above) were not well received. Please externalize your development trajectory and priorities for the benefit of the community. A simple check list worked reasonably well for eg Sayma hardware testing #224 and got some traction with DRTIO m-labs/artiq#562.

Why do you want it in the ARTIQ repository?

@jordens said in #3 "Ack. Gateware and firmware can be tracked in artiq." As a bridge between Sayma and ARTIQ consider using the ARTIQ repo sayma tag https://github.com/m-labs/artiq/labels/area%3Asayma.

[hartytp]

My preferred way of handling this is to create an ARTIQ issue for each item that's funded. cf issues like 687. I'll post issues for other items we've funded (e.g. Novogorny Urukul servo) soon.

[sbourdeauducq]

Yes, one issue per item sounds good. Many already exist.

[jbqubit]

@hartytp I agree. One Issue per item is a good approach. @sbourdeauducq please do this for the UMD/ARL contracts. And choose a unifying tag and/or milestone.

[jbqubit]

@sbourdeauducq @jordens How do you want to handle this for UMD/ARL contracts? I'm happy to create Issues as @hartytp did but I run the risk of dictating your workflow. Please comment.

[hartytp]

AFAICT, this has been done now.

[jbqubit]

Yes. Thank you @sbourdeauducq and @jordens.

4.0 mile stones -- Sayma baseline support
https://github.com/m-labs/artiq/milestone/11

5.0 mile stones -- extended Sayma support
https://github.com/m-labs/artiq/milestone/14