Requires a sufficiently up-to-date CPLD gateware.

This is prerequisite for phase coherent operation of SUServo.
The I/O update alignment delays can be configured by writing to servo
memory. The optimal io_update alignment delay and sync_in delay can be
found using the existing AD9910 (overloaded) methods, relying on
half-duplex CPLD readback capability.

Extension of the per-channel control interface by a flag en_pt, serving
to enable coherent DDS phase mode. This works by tracking the
DDS-internal phase accumulator as well as the servo runtime to calculate
the POW accordingly. The reference time for this calculation can be set
for each output channel individually in real time.