Note
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| ID | DESCRIPTION |
|---|---|
| 001 | Device shall include a minimum of one RP2040 integrated circuit. |
| 002 | Dimensions shall conform with PCI/104 form factor. |
| 003 | Device shall supply 1 external UART interface. |
| 004 | Device shall supply 1 external CAN interface. |
| 005 | Device shall supply 1 on-board SPI interface. |
| 006 | Device shall supply 1 on-board I2C interface. |
| 007 | Device shall use a TCXO to generate a stable reference clock. |
- UART (PHY TBD)
- CAN
- ARM CoreSight-10
The schematics for this project is laid out across multiple sheets. The top-level sheets contain functional block diagrams. The functional circuit blocks themselves are implemented in the lower-level sheets.
A 4-layer controlled impedance stackup is used.
| Layer | Designation |
|---|---|
| L1 (Top) | SIG |
| L2 | GND |
| L3 | GND |
| L3 (Bottom) | SIG+PWR |
Functional circuit blocks are routed first. The blocks are then laid out and connected.
High-speed electrical interfaces are routed with controlled impedance transmission lines.
Priority is given to routing high-speed interfaces.
Sensitive analog circuitry is separated from digital circuitry.
[1] CubeSat Information - CubeSat.org
[2] CubeSat Kit PCB Specification (archived from the original at http://www.cubesatkit.com/docs/CSK_PCB_Spec-A5.pdf)
[4]