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sevensegmentnew.syr
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Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s
--> Reading design: sevensegmentnew.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "sevensegmentnew.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "sevensegmentnew"
Output Format : NGC
Target Device : xc3s200-4-ft256
---- Source Options
Top Module Name : sevensegmentnew
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Write Timing Constraints : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
lso : sevensegmentnew.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "sevensegmentnew.v" in library work
Module <sevensegmentnew> compiled
No errors in compilation
Analysis of file <"sevensegmentnew.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <sevensegmentnew> in library <work>.
Building hierarchy successfully finished.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <sevensegmentnew>.
Module <sevensegmentnew> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <sevensegmentnew>.
Related source file is "sevensegmentnew.v".
WARNING:Xst:737 - Found 1-bit latch for signal <ss3_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss3_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss3_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss3_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss2_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss2_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss2_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss2_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss1_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss1_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss1_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss1_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss0_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss0_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss0_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <ss0_0>.
Unit <sevensegmentnew> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Latches : 16
1-bit latch : 16
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Latches : 16
1-bit latch : 16
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <sevensegmentnew> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sevensegmentnew, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : sevensegmentnew.ngr
Top Level Output File Name : sevensegmentnew
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 18
Cell Usage :
# BELS : 27
# LUT2 : 4
# LUT3 : 14
# LUT4 : 5
# MUXF5 : 4
# FlipFlops/Latches : 16
# LD : 16
# IO Buffers : 18
# IBUF : 7
# OBUF : 11
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 14 out of 1920 0%
Number of Slice Flip Flops: 16 out of 3840 0%
Number of 4 input LUTs: 23 out of 3840 0%
Number of IOs: 18
Number of bonded IOBs: 18 out of 173 10%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
w0(w01:O) | NONE(*)(ss0_1) | 4 |
w1(w11:O) | NONE(*)(ss1_3) | 4 |
w2(w21:O) | NONE(*)(ss2_2) | 4 |
w3(w31:O) | NONE(*)(ss3_3) | 4 |
-----------------------------------+------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: 1.941ns
Maximum output required time after clock: 12.841ns
Maximum combinational path delay: 13.609ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'w0'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 1.941ns (Levels of Logic = 1)
Source: x0 (PAD)
Destination: ss0_0 (LATCH)
Destination Clock: w0 falling
Data Path: x0 to ss0_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 0.821 0.917 x0_IBUF (x0_IBUF)
LD:D 0.203 ss0_0
----------------------------------------
Total 1.941ns (1.024ns logic, 0.917ns route)
(52.8% logic, 47.2% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'w1'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 1.941ns (Levels of Logic = 1)
Source: x0 (PAD)
Destination: ss1_0 (LATCH)
Destination Clock: w1 falling
Data Path: x0 to ss1_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 0.821 0.917 x0_IBUF (x0_IBUF)
LD:D 0.203 ss1_0
----------------------------------------
Total 1.941ns (1.024ns logic, 0.917ns route)
(52.8% logic, 47.2% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'w2'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 1.941ns (Levels of Logic = 1)
Source: x0 (PAD)
Destination: ss2_0 (LATCH)
Destination Clock: w2 falling
Data Path: x0 to ss2_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 0.821 0.917 x0_IBUF (x0_IBUF)
LD:D 0.203 ss2_0
----------------------------------------
Total 1.941ns (1.024ns logic, 0.917ns route)
(52.8% logic, 47.2% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'w3'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 1.941ns (Levels of Logic = 1)
Source: x0 (PAD)
Destination: ss3_0 (LATCH)
Destination Clock: w3 falling
Data Path: x0 to ss3_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 0.821 0.917 x0_IBUF (x0_IBUF)
LD:D 0.203 ss3_0
----------------------------------------
Total 1.941ns (1.024ns logic, 0.917ns route)
(52.8% logic, 47.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'w0'
Total number of paths / destination ports: 34 / 7
-------------------------------------------------------------------------
Offset: 12.841ns (Levels of Logic = 6)
Source: ss0_1 (LATCH)
Destination: f<5> (PAD)
Source Clock: w0 falling
Data Path: ss0_1 to f<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.633 0.996 ss0_1 (ss0_1)
LUT3:I1->O 1 0.551 0.000 d1_F (N40)
MUXF5:I0->O 7 0.360 1.405 d1 (d1)
LUT4:I0->O 1 0.551 0.000 _or000311_F (N46)
MUXF5:I0->O 5 0.360 0.989 _or000311 (N12)
LUT3:I2->O 1 0.551 0.801 _and00001 (f_2_OBUF)
OBUF:I->O 5.644 f_2_OBUF (f<2>)
----------------------------------------
Total 12.841ns (8.650ns logic, 4.191ns route)
(67.4% logic, 32.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'w2'
Total number of paths / destination ports: 34 / 7
-------------------------------------------------------------------------
Offset: 12.714ns (Levels of Logic = 6)
Source: ss2_1 (LATCH)
Destination: f<5> (PAD)
Source Clock: w2 falling
Data Path: ss2_1 to f<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.633 0.869 ss2_1 (ss2_1)
LUT3:I2->O 1 0.551 0.000 d1_F (N40)
MUXF5:I0->O 7 0.360 1.405 d1 (d1)
LUT4:I0->O 1 0.551 0.000 _or000311_F (N46)
MUXF5:I0->O 5 0.360 0.989 _or000311 (N12)
LUT3:I2->O 1 0.551 0.801 _and00001 (f_2_OBUF)
OBUF:I->O 5.644 f_2_OBUF (f<2>)
----------------------------------------
Total 12.714ns (8.650ns logic, 4.064ns route)
(68.0% logic, 32.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'w1'
Total number of paths / destination ports: 34 / 7
-------------------------------------------------------------------------
Offset: 12.841ns (Levels of Logic = 6)
Source: ss1_1 (LATCH)
Destination: f<5> (PAD)
Source Clock: w1 falling
Data Path: ss1_1 to f<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.633 0.996 ss1_1 (ss1_1)
LUT3:I1->O 1 0.551 0.000 d1_G (N41)
MUXF5:I1->O 7 0.360 1.405 d1 (d1)
LUT4:I0->O 1 0.551 0.000 _or000311_F (N46)
MUXF5:I0->O 5 0.360 0.989 _or000311 (N12)
LUT3:I2->O 1 0.551 0.801 _and00001 (f_2_OBUF)
OBUF:I->O 5.644 f_2_OBUF (f<2>)
----------------------------------------
Total 12.841ns (8.650ns logic, 4.191ns route)
(67.4% logic, 32.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'w3'
Total number of paths / destination ports: 34 / 7
-------------------------------------------------------------------------
Offset: 12.714ns (Levels of Logic = 6)
Source: ss3_1 (LATCH)
Destination: f<5> (PAD)
Source Clock: w3 falling
Data Path: ss3_1 to f<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.633 0.869 ss3_1 (ss3_1)
LUT3:I2->O 1 0.551 0.000 d1_G (N41)
MUXF5:I1->O 7 0.360 1.405 d1 (d1)
LUT4:I0->O 1 0.551 0.000 _or000311_F (N46)
MUXF5:I0->O 5 0.360 0.989 _or000311 (N12)
LUT3:I2->O 1 0.551 0.801 _and00001 (f_2_OBUF)
OBUF:I->O 5.644 f_2_OBUF (f<2>)
----------------------------------------
Total 12.714ns (8.650ns logic, 4.064ns route)
(68.0% logic, 32.0% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 110 / 11
-------------------------------------------------------------------------
Delay: 13.609ns (Levels of Logic = 7)
Source: sel0 (PAD)
Destination: f<5> (PAD)
Data Path: sel0 to f<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 16 0.821 1.576 sel0_IBUF (sel0_IBUF)
LUT3:I0->O 1 0.551 0.000 d1_F (N40)
MUXF5:I0->O 7 0.360 1.405 d1 (d1)
LUT4:I0->O 1 0.551 0.000 _or000311_F (N46)
MUXF5:I0->O 5 0.360 0.989 _or000311 (N12)
LUT3:I2->O 1 0.551 0.801 _and00001 (f_2_OBUF)
OBUF:I->O 5.644 f_2_OBUF (f<2>)
----------------------------------------
Total 13.609ns (8.838ns logic, 4.771ns route)
(64.9% logic, 35.1% route)
=========================================================================
CPU : 6.25 / 6.72 s | Elapsed : 6.00 / 6.00 s
-->
Total memory usage is 130268 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of infos : 1 ( 0 filtered)