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sevensegmentnew_map.mrp
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sevensegmentnew_map.mrp
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Release 8.2i Map I.31
Xilinx Mapping Report File for Design 'sevensegmentnew'
Design Information
------------------
Command Line : C:\Xilinx\bin\nt\map.exe -ise
E:/sevensegmentnew/sevensegmentnew.ise -intstyle ise -p xc3s200-ft256-4 -cm area
-pr b -k 4 -c 100 -o sevensegmentnew_map.ncd sevensegmentnew.ngd
sevensegmentnew.pcf
Target Device : xc3s200
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.34.32.1 $
Mapped Date : Fri Oct 25 10:10:26 2019
Design Summary
--------------
Number of errors: 0
Number of warnings: 6
Logic Utilization:
Number of Slice Latches: 8 out of 3,840 1%
Number of 4 input LUTs: 23 out of 3,840 1%
Logic Distribution:
Number of occupied Slices: 16 out of 1,920 1%
Number of Slices containing only related logic: 16 out of 16 100%
Number of Slices containing unrelated logic: 0 out of 16 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 23 out of 3,840 1%
Number of bonded IOBs: 18 out of 173 10%
IOB Latches: 8
Total equivalent gate count for design: 230
Additional JTAG gate count for IOBs: 864
Peak Memory Usage: 135 MB
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network N48 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
more times for the following (max. 5 shown):
N49
To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:372 - Gated clock. Clock net w1 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net w0 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net w3 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net w2 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) removed
2 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal "N48" is loadless and has been removed.
Loadless block "XST_GND" (ZERO) removed.
The signal "N49" is loadless and has been removed.
Loadless block "XST_VCC" (ONE) removed.
Section 6 - IOB Properties
--------------------------
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| WE | IOB | INPUT | LVCMOS25 | | | | | |
| f<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| f<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| f<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| f<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| f<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| f<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| f<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sel0 | IOB | INPUT | LVCMOS25 | | | | | |
| sel1 | IOB | INPUT | LVCMOS25 | | | | | |
| sw<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sw<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sw<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sw<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| x0 | IOB | INPUT | LVCMOS25 | | | INLATCH1 | | IFD |
| | | | | | | INLATCH2 | | |
| x1 | IOB | INPUT | LVCMOS25 | | | INLATCH1 | | IFD |
| | | | | | | INLATCH2 | | |
| x2 | IOB | INPUT | LVCMOS25 | | | INLATCH1 | | IFD |
| | | | | | | INLATCH2 | | |
| x3 | IOB | INPUT | LVCMOS25 | | | INLATCH1 | | IFD |
| | | | | | | INLATCH2 | | |
+------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings